Abstract: A nonvolatile memory device includes at least one first universal interface bus (UIB) circuit coupled to a plurality of input/output (I/O) pads, at least one second UIB circuit coupled to the plurality of I/O pads, a core block including a first input terminal coupled to another block, and a plurality of second input terminals coupled to a first output terminal of the at least one first UIB circuit and a second output terminal of the at least one second UIB circuit, and at least one block configured to activate the at least one second UIB circuit.

Abstract: An integrated circuit may include a plurality of combinational logic circuits including a first combinational logic circuit, a plurality of flip-flops including a first flip-flop configured to receive a first scan input signal and a first data signal, and a first core block including a multiplexer. The multiplexer may be configured to select, based on a test control signal, one of a primary input signal received through a primary input terminal and an output signal of the first flip-flop and provide the selected signal to the first combinational logic circuit. The first flip-flop may be further configured to selectively receive, based on a scan control signal, one of the first scan input signal and the first data signal.

Abstract: An integrated circuit includes: (i) a first block containing a first wrapper and a first area of circuit elements isolated by the first wrapper, (ii) a core logic circuit containing a target block, which includes a second wrapper and a second area of circuit elements isolated by the second wrapper, and a third wrapper and a third area of circuit elements isolated by the third wrapper, and (iii) a second block containing a fourth wrapper and a fourth area isolated by the fourth wrapper. The second wrapper is connected in series with the first wrapper, and is configured to support performance of a test operation on the second area. The third wrapper is connected in series with the fourth wrapper, and is configured to support performance of a test operation on the third area.