Abstract: A method and apparatus for provisioning broadband services to subscribers using an impedance-matched interface at a servicing area interface (SAI) that is in the same geographic vicinity as the subscriber group. Adequate signal-to-noise ratios at the subscriber site is achieved using a fraction of the power required using currently available broadband provisioning techniques. The impedance characteristics of the F1/F2 distribution lines at the SAI allow the broadband distribution system of the present invention to be deployed without the need for a POTS splitter to provide standard telephone service to the subscriber. The present invention also provides an improved coupling system to ensure that proper impedance is maintained to facilitate the operation of POTS equipment if the system components in the coupling system experience a loss of power.

Abstract: An inductor and transformer comprise a plurality of interleaved conductive layers and insulation layers fabricated on a monolithic semiconductor integrated circuit die. The conductive layers are shaped into coil turns of the inductor and the transformer, and are stacked vertically (perpendicular to the horizontal plane of the coil layers) and proximate to one another so as to achieve close magnetic coupling therebetween, thereby achieving a larger inductance value for a given sized coil structure. The conductive layer coil turns are connected together with conductive vias through the interposing insulation layers.

Abstract: Described herein is a network interface for coupling residential appliances into a code-division multiple access (CDMA) network. The network is used to convey appliance control signals and appliance status signals. The network interface includes a transmitter and/or a receiver, depending on the communications needs of the residential appliance. A spreading-code generator in the network interface generates a spreading code that identifies the residential appliance. A spreading mixer modulates a narrowband transmit signal with the spreading code, thereby generating a spread-spectrum transmit signal. The wideband transmit signal is then coupled into the physical medium of the network. In one embodiment, the physical medium is a residential wiring grid, and a wiring interface in the transmitter unit couples the spreading mixer with the residential wiring. Spread-spectrum signals received from the wiring grid are despread with an appropriate spreading code to extract the desired signal.

Abstract: A computing device, such as a laptop personal computer (PC), a desktop PC, or a personal information device (PID), includes an antenna embedded therein for wireless communications. The antenna may be formed on a printed circuit board installed in the computing device. The antenna may include multiple radiating and receiving elements for mitigating multipath effects and/or responding to steering circuitry to form a directed antenna beam.

Abstract: A digital communication system includes a receiver and a transmitter in communication with the receiver over a communication link. The transmitter includes a buffer circuit which receives input data signals for transmission and a control signal. The buffer circuit outputs buffered data signals. A symbol encoder circuit receives the buffered data signals and provides the control signal. The symbol encoder circuit outputs data symbols over the communication link. The buffered data signals are supplied to the symbol encoder circuit in accordance with the control signal. The data symbols may be encoded with a number of data bits. The encoding may be done by voltage-level encoding.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction.

Abstract: The present invention comprises a system and method for a GSM receiver to perform channel estimation under the assumption that the analog-to-digital (A/D) converter is free-running. A search process is employed, whereby the known GSM training signal is sampled with a plurality of phases which vary incrementally from zero to a full symbol period. For each phase a sample set (of the training signal) is generated. Furthermore, each sample set is used, together with the received samples, in a cross-correlation procedure to obtain a candidate impulse response vector for the transmission channel. Thus a plurality of candidate impulse response vectors are produced, one of which will be selected to be the optimal representative for the transmission channel. The optimal impulse response vector is selected as follows. Each impulse response vector is convolved with the corresponding sample set, thus producing an estimated output vector.

Abstract: A method of processing incoming ethernet frames includes the steps of storing a header of each incoming ethernet frame in a header column of a buffer array, storing a data field of each incoming ethernet frame in a data column of the buffer array, each data field being stored in a same row of the buffer array as a corresponding header, and storing a CRC of each incoming ethernet frame in a CRC column which is next to the header column, each CRC being stored in a same row of the buffer array as a corresponding header and a corresponding data field. The method can further include the step of evaluating each stored CRC based on the header stored next to the CRC. In one alternative, the header column is between the CRC column and the data column. In another alternative, the CRC column is between the header column and the data column.

Abstract: A modulated bus interconnects each of the plurality of elements on the bus through a filter having a center frequency corresponding to a carrier frequency which modulated by digital information destined for the particular device. Since the device receives an incoming message through a filter, it detects only those messages which have the appropriate filter characteristics. In order to send a message to another device, the first device must apply the appropriate carrier. Thus, multiple transfers between multiple devices can take place simultaneously on a wide-band transmission medium. A controller can be used to dynamically allocate the bus according to an efficient allocation scheme.

Abstract: A method of communicating a video image via an audio communication signal includes the steps of identifying, for a given pixel location of the video image, a set of samples within a stored audio signal having a corresponding bit pattern, generating a marker identifying the location of the given pixel in the video image, and multiplexing the stored audio signal and the marker such that the marker appears within the stored audio signal proximate to the set of samples having the corresponding bit pattern. This method can also include the steps of transmitting the multiplexed signal to a destination device, demultiplexing, at the destination device, to recover the marker and the corresponding bit pattern, illuminating a display at the given pixel location according to the corresponding bit pattern, and converting the corresponding bit pattern into an analog audio signal.

Abstract: A digital voice data storage and retrieval system using a low bit rate encoder which provides enhanced speech signal quality while also reducing memory size requirements. The system comprises a voice coder/decoder which preferably includes a digital signal processor (DSP) and also preferably includes a local memory. During encoding of the voice data, the voice coder/decoder receives voice input waveforms and generates a parametric representation of the voice data. A storage memory is coupled to the voice coder/decoder for storing the parametric data. During decoding of the voice data, the voice coder/decoder receives the parametric data from the storage memory and reproduces the voice waveforms. According to the invention, an interframe smoothing method is performed on the parametric data after encoding of all of the speech data has completed and the parametric data has been stored in the storage memory.

Abstract: A method of executing a program includes reading a next operation of an executing program and determining if a given pointer corresponding to the next operation is stored in a pointer table. If the given pointer is stored in the pointer table, an instruction identified by the given pointer is executed in a processor. However, if the given pointer is not stored in the pointer table, a replaceable pointer in the pointer table is identified and replaced by the given pointer. Instructions corresponding to the given pointer are also imported into a processor instruction unit from a supplemental storage area and subsequently executed by the processor. The instructions can comprise microcode or a portion of a programmable gate array. In the latter case, the supplemental storage area can store gate array programming instructions for use in reprogramming the instructions in the processor.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, an also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems.

Abstract: A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X8 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a look-up table which stores instruction sequences which implement DSP functions. Each pattern in the look-up table is compared with an instruction sequence to determine if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the DSP function preprocessor converts the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems.

Abstract: A servo loop control apparatus having a master microprocessor and at least one autonomous streamlined signal processor is disclosed. The architecture provides a general purpose controller for use in systems where intensive servo signal processing is required and is well suited to applications where multiple servo control loops operate simultaneously. The operation of the streamlined signal processors is autonomous from the master processor so that critical functions can be dedicated to the streamlined signal processors. This eliminates complex interrupt management and tedious real time scheduling constraints, simplifies system design and improves system performance. The architecture provides an integrated mechanism for implementing multiple, concurrent, complex signal processing and embedded control functions, such as complete servo-mechanism management for high performance disk storage systems.

Abstract: A servo loop control apparatus having a master microprocessor and at least one autonomous streamlined signal processor is disclosed. The architecture provides a general purpose controller for use in systems where intensive servo signal processing is required and is well suited to applications where multiple servo control loops operate simultaneously. The operation of the streamlined signal processors is autonomous from the master processor so that critical functions can be dedicated to the streamlined signal processors. This eliminates complex interrupt management and tedious real time scheduling constraints, simplifies system design and improves system performance. The architecture provides an integrated mechanism for implementing multiple, concurrent, complex signal processing and embedded control functions, such as complete servo-mechanism management for high performance disk storage systems.

Abstract: A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a pattern recognition detector which stores instruction sequences which implement DSP functions. The pattern recognition detector compares each pattern with an instruction sequence and determines if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the preprocessor converts or maps the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction.