Patents by Inventor Safak Sayan
Safak Sayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230359116Abstract: The present disclosure is directed to a membrane cleaning system and a membrane cleaning process, the membrane cleaning system including: a membrane; a membrane holder accommodating the membrane in a cut-out section within the membrane holder, wherein the cut-out section allows access to the membrane from two opposing sides; and a speaker configured to emit sound waves of a resonant frequency of the membrane for a predetermined duration and at a predetermined amplitude, wherein the sound waves are directed to one side of the membrane.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Inventors: Safak SAYAN, Jae Young KANG, Abdolreza JAVADI, Srinath SATYANARAYANA, Herbert HSU, Christopher KAPLAN
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Patent number: 10303048Abstract: The present disclosure relates to a patterned structure, the structure comprising: i) a substrate, ii) a first layer on top of the substrate, comprising a filler material and a guiding material, wherein at least a top surface of the first layer comprises one or more zones of filler material and one or more zones of guiding material, and iii) a second layer on top of the first layer comprising a pattern of a first material, the pattern being either aligned or anti-aligned with the underlying one or more zones of guiding material; wherein the first material comprises a metal or a ceramic material and wherein the guiding material and the filler material either both comprise or both do not comprise the metal or ceramic material.Type: GrantFiled: February 15, 2017Date of Patent: May 28, 2019Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&DInventors: Boon Teik Chan, Arjun Singh, Safak Sayan
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Patent number: 10192956Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.Type: GrantFiled: July 7, 2016Date of Patent: January 29, 2019Assignee: IMEC VZWInventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
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Patent number: 9905455Abstract: A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique.Type: GrantFiled: October 21, 2015Date of Patent: February 27, 2018Assignee: IMEC VZWInventors: Boon Teik Chan, Safak Sayan
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Publication number: 20170242335Abstract: The present disclosure relates to a patterned structure, the structure comprising: i) a substrate, ii) a first layer on top of the substrate, comprising a filler material and a guiding material, wherein at least a top surface of the first layer comprises one or more zones of filler material and one or more zones of guiding material, and iii) a second layer on top of the first layer comprising a pattern of a first material, the pattern being either aligned or anti-aligned with the underlying one or more zones of guiding material; wherein the first material comprises a metal or a ceramic material and wherein the guiding material and the filler material either both comprise or both do not comprise the metal or ceramic material.Type: ApplicationFiled: February 15, 2017Publication date: August 24, 2017Applicants: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&DInventors: Boon Teik Chan, Arjun Singh, Safak Sayan
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Patent number: 9548208Abstract: A method for patterning an underlying layer is described, the method comprising providing a guiding layer on the underlying layer, the guiding layer comprising guiding structures and being substantially planar; providing a block-copolymer layer on the guiding layer; inducing phase separation of the block-copolymer layer in a regular pattern of structures of a first and a second polymer component, whereby one of the components aligns to the guiding structures, by chemo-epitaxy; thereafter, removing a first of the components of the block-copolymer layers completely, leaving a regular pattern of structures of the second component; providing a planarizing layer over the regular pattern of structures of the second component and the guiding layer; removing a portion of the planarizing layer, thereby leaving a regular pattern of structures of the planarizing layer at positions in between the structures of the second component, and exposing the structures of the second component; removing the structures of the secondType: GrantFiled: February 17, 2016Date of Patent: January 17, 2017Assignee: IMEC VZWInventors: Boon Teik Chan, Zheng Tao, Nadia Vandenbroeck, Safak Sayan
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Publication number: 20160322461Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.Type: ApplicationFiled: July 7, 2016Publication date: November 3, 2016Applicant: IMEC VZWInventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
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Publication number: 20160254161Abstract: A method for patterning an underlying layer is described, the method comprising providing a guiding layer on the underlying layer, the guiding layer comprising guiding structures and being substantially planar; providing a block-copolymer layer on the guiding layer; inducing phase separation of the block-copolymer layer in a regular pattern of structures of a first and a second polymer component, whereby one of the components aligns to the guiding structures, by chemo-epitaxy; thereafter, removing a first of the components of the block-copolymer layers completely, leaving a regular pattern of structures of the second component; providing a planarizing layer over the regular pattern of structures of the second component and the guiding layer; removing a portion of the planarizing layer, thereby leaving a regular pattern of structures of the planarizing layer at positions in between the structures of the second component, and exposing the structures of the second component; removing the structures of the secondType: ApplicationFiled: February 17, 2016Publication date: September 1, 2016Applicant: IMEC VZWInventors: Boon Teik Chan, Zheng Tao, Nadia Vandenbroeck, Safak Sayan
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Patent number: 9391141Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.Type: GrantFiled: February 23, 2015Date of Patent: July 12, 2016Assignee: IMEC VZWInventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
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Publication number: 20160118295Abstract: A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique.Type: ApplicationFiled: October 21, 2015Publication date: April 28, 2016Applicant: IMEC VZWInventors: Boon Teik Chan, Safak Sayan
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Publication number: 20150243509Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.Type: ApplicationFiled: February 23, 2015Publication date: August 27, 2015Applicant: IMEC VZWInventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
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Publication number: 20070232074Abstract: Embodiments of methods of forming a high thermal conductivity diamond film on a substrate using at least two different average particle sizes of diamond for nucleation and its associated structures.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Inventors: Kramadhati Ravi, Safak Sayan