Patents by Inventor Sagar C. Pawar

Sagar C. Pawar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134445
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Application
    Filed: October 29, 2023
    Publication date: April 25, 2024
    Inventors: Ravindra A. Babu, Sashank Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Publication number: 20240111560
    Abstract: Embodiments herein relate to providing uniform servicing of workloads at a set of servers in a computer network. A platform determines and meets the performance requirements of a workload by scaling a performance capability of a group of processing units such as central processing units (CPUs) which are assigned to service the workload. This can involve increasing the power (P) state of one or more of the processing units to a highest P state in the group, so that every processing units in the group provides the same performance for a given workload. The platform can manage scaling of the processing units performance by reading a performance profile list which indicates minimum and maximum scaling points for programs that are executed to service the workload.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Subhankar Panda, Rupal M. Parikh, Gaurav Porwal, Raghavendra Nagaraj, Sagar C. Pawar, Prakash Pillai
  • Patent number: 11907416
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Ravindra A. Babu, Sashank Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Publication number: 20240004454
    Abstract: In an embodiment, a processor may include processing circuits to execute instructions. The processor may also include at least one circuit to: detect a management mode trigger event during operation of the processor in a first power state, the management mode trigger event to initiate a management mode in the processor; in response to a detection of the management mode trigger event, switch the processor from the first power state to a second power state; and after a switch of the processor from the first power state to the second power state, initiate the management mode in the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Sagar C. Pawar, Pannerkumar Rajagopal, Raghavendra Nagaraj, Ovais F. Pir, Prakash Pillai
  • Patent number: 11800083
    Abstract: Systems, apparatuses and methods may provide for technology that includes a substrate, and a display pipeline coupled to the substrate. The display pipeline may to barrel an initial image to form a barreled image.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Ravindra A. Babu, Sagar C. Pawar, Satyanantha R. Musunuri, Sashank Ms, Kalyan K. Kaipa
  • Publication number: 20230315198
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Application
    Filed: March 10, 2023
    Publication date: October 5, 2023
    Inventors: Ravindra A. Babu, Sashank Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Patent number: 11720401
    Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Pannerkumar Rajagopal, Murali R Iyengar, Karunakara Kotary, Ovais Pir, Sagar C Pawar, Prakash Pillai, Raghavendra N, Aneesh A Tuljapurkar
  • Patent number: 11650658
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Ravindra A. Babu, Sashank Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Patent number: 11619987
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Ravindra A. Babu, Sashank Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Publication number: 20220391003
    Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.
    Type: Application
    Filed: March 23, 2022
    Publication date: December 8, 2022
    Inventors: Pannerkumar Rajagopal, Raghavendra N, Ovais Pir, Prakash Pillai, Sagar C. Pawar
  • Publication number: 20220224877
    Abstract: Systems, apparatuses and methods may provide for technology that includes a substrate, and a display pipeline coupled to the substrate. The display pipeline may to barrel an initial image to form a barreled image.
    Type: Application
    Filed: November 19, 2021
    Publication date: July 14, 2022
    Applicant: Intel Corporation
    Inventors: Ravindra A. Babu, Sagar C. Pawar, Satyanantha R. Musunuri, Sashank Ms, Kalyan K. Kaipa
  • Publication number: 20220198022
    Abstract: A power-up scheme for a computing system that applies a biometric sensor (e.g., a fingerprint sensor, eye sensor, etc.) to authenticate a user before enabling power-up of the computing system or to resume transition to a power state (e.g., one of the power states defined by the Advance Configuration and Power Interface (ACPI)). Output of the biometric sensor is compared against data of a registered user for a match. The data may include an original copy of an output of the biometric sensor saved in a non-volatile memory (e.g., serial peripheral interface (SPI) flash device). If a match exists, a logic in the computing system will allow the computing system to power-up. In the absence of a match, the computing system will not be powered up. In some examples, battery charging is also disabled if the match is not found.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Sagar C. Pawar, Pannerkumar Rajagopal, Raghavendra N, Prakash Pillai, Ovais Pir
  • Patent number: 11281764
    Abstract: In some examples, an apparatus to authenticate a battery includes a battery voltage monitor to monitor a voltage of the battery. The apparatus to authenticate the battery also includes a voltage source regulator to filter the voltage of the battery and provide the filtered voltage to turn on circuitry to be used to authenticate the battery.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 22, 2022
    Assignee: INTEL CORPORATION
    Inventors: Sagar C. Pawar, Panner Kumar, Karunakara Kotary, Ovais F. Pir
  • Patent number: 11237626
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Ravindra A. Babu, Sashank Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Patent number: 11206390
    Abstract: Systems, apparatuses and methods may provide for technology that includes a substrate, and a display pipeline coupled to the substrate. The display pipeline may to barrel an initial image to form a barreled image.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Ravindra A. Babu, Sagar C. Pawar, Satyanantha R. Musunuri, Sashank Ms, Kalyan K. Kaipa
  • Publication number: 20200410084
    Abstract: In some examples, an apparatus to authenticate a battery includes a battery voltage monitor to monitor a voltage of the battery. The apparatus to authenticate the battery also includes a voltage source regulator to filter the voltage of the battery and provide the filtered voltage to turn on circuitry to be used to authenticate the battery.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sagar C. Pawar, Panner Kumar, Karunakara Kotary, Ovais F. Pir
  • Publication number: 20200341545
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Inventors: Ravindra A. Babu, Sashank Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Publication number: 20200301503
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Application
    Filed: May 7, 2020
    Publication date: September 24, 2020
    Inventors: Ravindra A. Babu, Sashank Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Patent number: 10769747
    Abstract: Systems, apparatuses and methods may provide for technology that includes a microcontroller to control a workload of a graphics processor, to determine if at least one predetermined condition is met, and instruct, if the at least one predetermined condition is met, the graphics processor to transform an initial frame into an intermediate frame.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Ravindra A. Babu, Satyanantha R. Musunuri, Sashank Ms, Sagar C. Pawar, Kalyan K. Kaipa
  • Patent number: 10747779
    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Sagar C. Pawar, Prakash Pillai, Raghavendra N, Aneesh A. Tuljapurkar