Patents by Inventor Sagar NATARAJ

Sagar NATARAJ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10891884
    Abstract: Design-for-test (DFT) architectures, and methods of testing an array of chips, which may be identical, are described. In an embodiment, a comparison circuit includes a plurality of comparators to compare scan-data out (SDO) data streams with an expected data stream and transmit a compared data stream that is indicated of whether or not an error exists in any of the SDO data streams.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: January 12, 2021
    Assignee: Apple Inc.
    Inventors: Bo Yang, Xiang Lu, Andrew J. Copperhall, Henry C. Jen, Karthik Manickam, Sagar Nataraj, Shriram Vijayakumar, Derek K. Shaeffer
  • Patent number: 9500706
    Abstract: Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: November 22, 2016
    Assignee: NVIDIA Corporation
    Inventors: Amit Sanghani, Sagar Nataraj, Karthikeyan Natarajan, Bo Yang
  • Publication number: 20150204945
    Abstract: Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 23, 2015
    Applicant: NVIDIA Corporation
    Inventors: Amit SANGHANI, Sagar NATARAJ, Karthikeyan NATARAJAN, Bo YANG