Patents by Inventor Sagar Trivedi

Sagar Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230384690
    Abstract: A method of manufacturing a photo mask includes determining an enhancement region, in a simulation zone, of a layout pattern of a photo mask. The method includes determining a stitching mobility zone inside the simulation zone, determining an optimization mobility zone inside the stitching mobility zone, and performing an inverse lithographic transformation (ILT) operation of the layout pattern in the simulation zone to generate an ILT adjusted layout pattern in the simulation zone. The method includes combining a weighted sum of the ILT adjusted layout pattern and the layout pattern in the simulation zone to generate an enhanced layout pattern of the photo mask in the simulation zone using a first weighting function inside enhancement region, a second weighting function between boundaries of the enhancement region and the optimization mobility zone, and a third weighting function between boundaries of the optimization mobility zone and the stitching mobility zone.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Sagar TRIVEDI, Daniel Beylkin
  • Patent number: 11747786
    Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
  • Publication number: 20220299884
    Abstract: A method of manufacturing a photo mask includes determining an enhancement region, in a simulation zone, of a layout pattern of a photo mask. The method includes determining a stitching mobility zone inside the simulation zone, determining an optimization mobility zone inside the stitching mobility zone, and performing an inverse lithographic transformation (ILT) operation of the layout pattern in the simulation zone to generate an ILT adjusted layout pattern in the simulation zone. The method includes combining a weighted sum of the ILT adjusted layout pattern and the layout pattern in the simulation zone to generate an enhanced layout pattern of the photo mask in the simulation zone using a first weighting function inside enhancement region, a second weighting function between boundaries of the enhancement region and the optimization mobility zone, and a third weighting function between boundaries of the optimization mobility zone and the stitching mobility zone.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventors: Sagar TRIVEDI, Daniel BEYLKIN
  • Publication number: 20220291659
    Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 15, 2022
    Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
  • Patent number: 11340584
    Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
  • Publication number: 20210181713
    Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 17, 2021
    Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
  • Patent number: 10915090
    Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
  • Publication number: 20200293023
    Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu