Abstract: For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

Abstract: Program verify can be performed simultaneously on multiple subblocks in a storage device. The program verify occurs after a program operation of the storage cells. The program verify can include application of a verify read pulse to multiple subblocks simultaneously and then a count a number of bitlines of the multiple subblocks that do not discharge in response to the verify read pulse. The program verify passes if the count is within an expected range, instead of requiring all storage cells to pass program verify before moving on. If the number of bitlines not discharging is outside the expected range, the system can perform a second program pass.

Abstract: A storage device charges bitlines in preparation for a program pulse. To charge the bitlines, the storage device connects the bitlines to an external regulator instead of an internal regulator to prepare them for the program pulse. The system can charge all bitlines to the external regulator high voltage reference before changing to the internal regulator for bitline stabilization before the program pulse.

Abstract: Methods and apparatus for fast and efficient verify recovery and array discharge for 3D NAND memory arrays and other 3D storage devices. The 3D storage device includes storage arrays including strings of memory cells stacked on top of one another and sharing a channel in a pillar for the string. The memory cells for a string occupy respective tiers in a 3D structure with each tier having an associated wordline. A controller is used to program charge levels in the memory cells. Programming is followed by a fast verify recovery where a voltage is applied to the wordlines to perform a program verify, followed by discharging wordlines. Erased wordlines are identified and discharged first, followed by programmed wordlines, which may employ staggered discharge sequences. Dummy wordlines are then discharged, with an optional timer delay. For multi-deck devices, wordlines in the deck with an active wordline are discharged before wordlines in one or more other decks.

Abstract: NAND performance is increased by reducing the time to perform program operations. An operation to program a portion of NAND cells in a NAND memory array includes multiple stages. NAND performance is increased by reducing the time in a first stage of the multiple stages to compute parameters that are used in a second stage to perform program operation(s) and verify operation(s). The time in the first stage is reduced by enabling dynamic prologue selection to dynamically select one of multiple sets of first stage operations to be performed in the first stage for a program operation based on the Word Line (WL), WL-Group, and block information for a current program operation and a previous program operation.

Abstract: Methods and apparatus for Enhanced IO Interface for PLC program and program-suspend-resume operations. A NAND memory device includes blocks of single-level cell (SLC) memory and multi-level cell (MLC) memory storing n-bits per cell such as quad-level cell (QLC) or penta-level cell (PLC) memory. The NAND memory device further includes a plurality of page buffer latches and logic to copy data from a set of n SLC pages in a block of SLC memory into n respective page buffer latches and copy data from the respective page buffer latches to an MLC page (e.g., QLC or PLC page) in a block of MLC memory. These operations can be extended for NAND memory devices having multiple planes with blocks of SLC and QLC/PLC memory. QLC/PLC program and program-resume operations are supported with optional ECC correction operations.

Abstract: Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (L1) of the MLC memory.

Abstract: For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

Abstract: A programming of a memory device configurable to reach a plurality of voltage levels is initiated. For each voltage level to be reached, a checkpoint is set up within a sequence of program pulses applied for the programming of the memory device, to determine whether a plurality of memory cells of the memory device have reached the voltage level. The programming of the memory device is aborted, in response to determining at the checkpoint that the plurality of memory cells have not reached the voltage level.