Patents by Inventor SAGAR V. DALVI
SAGAR V. DALVI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12236243Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.Type: GrantFiled: April 24, 2023Date of Patent: February 25, 2025Assignee: Intel CorporationInventors: Jason W. Brandt, Deepak K. Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell, Sergiu Ghetie, Wojciech Powiertowski, Jared W. Stark, IV, Ariel Sabba, Scott J. Cape, Hisham Shafi, Lihu Rappoport, Yair Berger, Scott P. Bobholz, Gilad Holzstein, Sagar V. Dalvi, Yogesh Bijlani
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Publication number: 20240296051Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.Type: ApplicationFiled: May 10, 2024Publication date: September 5, 2024Inventors: Jason W. Brandt, Deepak K. Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell, Sergiu Ghetie, Wojciech Powiertowski, Jared W. Stark, IV, Ariel Sabba, Scott J. Cape, Hisham Shafi, Lihu Rappoport, Yair Berger, Scott P. Bobholz, Gilad Holzstein, Sagar V. Dalvi, Yogesh Bijlani
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Patent number: 11838113Abstract: Embodiments are generally directed apparatuses, methods, techniques and so forth to receive a sled manifest comprising identifiers for physical resources of a sled, receive results of an authentication and validation operations performed to authenticate and validate the physical resources of the sled, determine whether the results of the authentication and validation operations indicate the physical resources are authenticate or not authenticate. Further and in response to the determination that the results indicate the physical resources are authenticated, permit the physical resources to process a workload, and in response to the determination that the results indicate the physical resources are not authenticated, prevent the physical resources from processing the workload.Type: GrantFiled: October 17, 2019Date of Patent: December 5, 2023Assignee: INTEL CORPORATIONInventors: Alberto J. Munoz, Murugasamy K. Nachimuthu, Mohan J. Kumar, Wojciech Powiertowski, Sergiu D. Ghetie, Neeraj S. Upasani, Sagar V. Dalvi, Chukwunenye S. Nnebe, Jeanne Guillory
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Publication number: 20230342156Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.Type: ApplicationFiled: April 24, 2023Publication date: October 26, 2023Inventors: Jason W. Brandt, Deepak K. Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell, Sergiu Ghetie, Wojciech Powiertowski, Jared W. Stark, IV, Ariel Sabba, Scott J. Cape, Hisham Shafi, Lihu Rappoport, Yair Berger, Scott P. Bobholz, Gilad Holzstein, Sagar V. Dalvi, Yogesh Bijlani
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Patent number: 11635965Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.Type: GrantFiled: October 31, 2018Date of Patent: April 25, 2023Assignee: Intel CorporationInventors: Jason W. Brandt, Deepak K. Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell, Sergiu D. Ghetie, Wojciech Powiertowski, Jared W. Stark, IV, Ariel Sabba, Scott J. Cape, Hisham Shafi, Lihu Rappoport, Yair Berger, Scott P. Bobholz, Gilad Holzstein, Sagar V. Dalvi, Yogesh Bijlani
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Publication number: 20220334825Abstract: An apparatus of a data center, a computer-readable medium, a method and a system. The apparatus includes one or more processors to: access first information corresponding to a firmware (FW) payload, the FW payload to identify a server FW component; access second information corresponding to FW update metadata, the FW update metadata to indicate one or more dependencies of a FW update of the server FW component; perform a validation of the one or more dependencies against corresponding server information; and in response to a determination of a success of the validation, communicate with an execution engine to cause execution of the FW update on the server.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Piotr K. Swirydczuk, Sagar V. Dalvi
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Patent number: 11468170Abstract: A processor can be configured to access boot firmware from a remote location independent from use of a chipset. After a processor powers-on or reboots, the processor can execute microcode. The microcode will cause the processor to train a link with a remote device. The remote device can provide the processor with access to boot firmware. The processor can copy the boot firmware to the processor's cache or memory. The processor will attempt to authenticate the boot firmware. If the boot firmware is authenticated, the processor executes the copy of the boot firmware.Type: GrantFiled: December 7, 2018Date of Patent: October 11, 2022Assignee: Intel CorporationInventors: Sergiu D. Ghetie, Wojciech Powiertowski, Jeanne Guillory, Neeraj S. Upasani, Srihari Narayanan, Mohan J. Kumar, Sagar V. Dalvi, Francisco Orlando C. Arbildo
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Patent number: 11392703Abstract: Embodiments detailed herein include, but are not limited to, a hardware processor to execute instructions and security circuitry to perform pre-boot operations including signature verification of a portion of firmware in a firmware storage hardware and initiating recovery upon a signature verification failure. The hardware processor comprises a plurality of cores in some embodiments. The hardware processor a multicore processor in some embodiments.Type: GrantFiled: December 10, 2019Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Sergiu D Ghetie, Neeraj S. Upasani, Sagar V. Dalvi, David P. Turley, Jeanne Guillory, Mark D. Chubb, Allen R. Wishman, Shahrokh Shahidzadeh
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Publication number: 20210357202Abstract: Examples described herein include a device, that when operational, is to: during an update of firmware for the device, execute a reduced function firmware to maintain operation of the device, wherein the reduced function firmware provides the device with less functionality than the updated firmware. In some examples, the reduced function firmware comprises a verified reduced function firmware. In some examples, the reduced function firmware comprises an updated version of a reduced function firmware that overwrites a full firmware in firmware storage.Type: ApplicationFiled: July 29, 2021Publication date: November 18, 2021Inventors: Piotr SWIRYDCZUK, Sagar V. DALVI
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Publication number: 20200133679Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: Jason W. Brandt, Deepak K. Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell, Sergiu Ghetie, Wojciech Powiertowski, Jared W. Stark, IV, Ariel Sabba, Scott J. Cape, Hisham Shafi, Lihu Rappoport, Yair Berger, Scott P. Bobholz, Gilad Holzstein, Sagar V. Dalvi, Yogesh Bijlani
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Publication number: 20200110880Abstract: Embodiments detailed herein include, but are not limited to, a hardware processor to execute instructions and security circuitry to perform pre-boot operations including signature verification of a portion of firmware in a firmware storage hardware and initiating recovery upon a signature verification failure. The hardware processor comprises a plurality of cores in some embodiments. The hardware processor a multicore processor in some embodiments.Type: ApplicationFiled: December 10, 2019Publication date: April 9, 2020Inventors: SERGIU D. GHETIE, NEERAJ S. UPASANI, SAGAR V. DALVI, DAVID P. TURLEY, JEANNE GUILLORY, MARK D. CHUBB, ALLEN R. WISHMAN, SHAHROKH SHAHIDZADEH
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Publication number: 20200053438Abstract: Embodiments are generally directed apparatuses, methods, techniques and so forth to receive a sled manifest comprising identifiers for physical resources of a sled, receive results of an authentication and validation operations performed to authenticate and validate the physical resources of the sled, determine whether the results of the authentication and validation operations indicate the physical resources are authenticate or not authenticate. Further and in response to the determination that the results indicate the physical resources are authenticated, permit the physical resources to process a workload, and in response to the determination that the results indicate the physical resources are not authenticated, prevent the physical resources from processing the workload.Type: ApplicationFiled: October 17, 2019Publication date: February 13, 2020Applicant: INTEL CORPORATIONInventors: ALBERTO J. MUNOZ, MURUGASAMY K. NACHIMUTHU, MOHAN J. KUMAR, WOJCIECH POWIERTOWSKI, SERGIU D. GHETIE, NEERAJ S. UPASANI, SAGAR V. DALVI, CHUKWUNENYE S. NNEBE, JEANNE GUILLORY
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Patent number: 10515218Abstract: Embodiments detailed herein include, but are not limited to, a hardware processor to execute instructions and security circuitry to perform pre-boot operations including signature verification of a portion of firmware in a firmware storage hardware and initiating recovery upon a signature verification failure. The hardware processor comprises a plurality of cores in some embodiments. The hardware processor a multicore processor in some embodiments.Type: GrantFiled: October 1, 2016Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Sergiu D Ghetie, Neeraj S. Upasani, Sagar V. Dalvi, David P. Turley, Jeanne Guillory, Mark D. Chubb, Allen R. Wishman, Shahrokh Shahidzadeh
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Patent number: 10489156Abstract: Embodiments are generally directed apparatuses, methods, techniques and so forth to receive a sled manifest comprising identifiers for physical resources of a sled, receive results of an authentication and validation operations performed to authenticate and validate the physical resources of the sled, determine whether the results of the authentication and validation operations indicate the physical resources are authenticate or not authenticate. Further and in response to the determination that the results indicate the physical resources are authenticated, permit the physical resources to process a workload, and in response to the determination that the results indicate the physical resources are not authenticated, prevent the physical resources from processing the workload.Type: GrantFiled: July 21, 2017Date of Patent: November 26, 2019Assignee: INTEL CORPORATIONInventors: Alberto J. Munoz, Murugasamy K. Nachimuthu, Mohan J. Kumar, Wojciech Powiertowski, Sergiu D. Ghetie, Neeraj S. Upasani, Sagar V. Dalvi, Chukwunenye S. Nnebe, Jeanne Guillory
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Publication number: 20190108347Abstract: A processor can be configured to access boot firmware from a remote location independent from use of a chipset. After a processor powers-on or reboots, the processor can execute microcode. The microcode will cause the processor to train a link with a remote device. The remote device can provide the processor with access to boot firmware. The processor can copy the boot firmware to the processor's cache or memory. The processor will attempt to authenticate the boot firmware. If the boot firmware is authenticated, the processor executes the copy of the boot firmware.Type: ApplicationFiled: December 7, 2018Publication date: April 11, 2019Inventors: Sergiu D. GHETIE, Wojciech POWIERTOWSKI, Jeanne GUILLORY, Neeraj S. UPASANI, Srihari NARAYANAN, Mohan J. KUMAR, Sagar V. DALVI
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Publication number: 20190065261Abstract: Technologies for providing in-processor workload phase detection include a sled having a compute engine, which itself includes a performance monitor unit. The compute engine obtains telemetry data from the performance monitor unit. The performance monitor unit produces telemetry data indicative of performance metrics of the sled during execution of one or more workloads. The telemetry data is indicative of a resource utilization and workload performance by the sled as the workloads are executed. The compute engine determines, from a lookup table indicative of resource utilization phases, a resource utilization phase based on the obtained telemetry data. A workload fingerprint is updated based on the determined resource utilization phase, and the workload fingerprint is output. Other embodiments are also described and claimed.Type: ApplicationFiled: December 30, 2017Publication date: February 28, 2019Inventors: Ananth S. Narayan, Sagar V. Dalvi, Mrittika Ganguli, Sergiu D. Ghetie
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Publication number: 20180096151Abstract: Embodiments detailed herein include, but are not limited to, a hardware processor to execute instructions and security circuitry to perform pre-boot operations including signature verification of a portion of firmware in a firmware storage hardware and initiating recovery upon a signature verification failure. The hardware processor comprises a plurality of cores in some embodiments. The hardware processor a multicore processor in some embodiments.Type: ApplicationFiled: October 1, 2016Publication date: April 5, 2018Inventors: SERGIU D GHETIE, NEERAJ S. UPASANI, SAGAR V. DALVI, DAVID P. TURLEY, JEANNE GUILLORY, MARK D. CHUBB, ALLEN R. WISHMAN, SHAHROKH SHAHIDZADEH
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Publication number: 20180097839Abstract: Embodiments detailed herein describe a system comprising a manageability server to generate an encrypted sideband message having at least one command; a server including: a radio frequency identification (RFID) device, the RFID device to include storage to store at least one encrypted sideband message having at least one command, and a security circuit coupled to the RFID device, the security circuit to: retrieve at least one encrypted sideband message from the RFID device storage, decrypt the one encrypted sideband message, determine validity of the decrypted sideband message using information from the decrypted sideband message, and perform an action in response to the at least one command.Type: ApplicationFiled: October 1, 2016Publication date: April 5, 2018Inventors: NEERAJ S. UPASANI, SAGAR V. DALVI, WOJCIECH POWIERTOWSKI, SERGIU D GHETIE, WON LEE, JEANNE GUILLORY, CHUKWUNENYE S. NNEBE
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Publication number: 20180026800Abstract: Embodiments are generally directed apparatuses, methods, techniques and so forth to receive a sled manifest comprising identifiers for physical resources of a sled, receive results of an authentication and validation operations performed to authenticate and validate the physical resources of the sled, determine whether the results of the authentication and validation operations indicate the physical resources are authenticate or not authenticate. Further and in response to the determination that the results indicate the physical resources are authenticated, permit the physical resources to process a workload, and in response to the determination that the results indicate the physical resources are not authenticated, prevent the physical resources from processing the workload.Type: ApplicationFiled: July 21, 2017Publication date: January 25, 2018Inventors: ALBERTO J. MUNOZ, MURUGASAMY K. NACHIMUTHU, MOHAN J. KUMAR, WOJCIECH POWIERTOWSKI, SERGIU D. GHETIE, NEERAJ S. UPASANI, SAGAR V. DALVI, CHUKWUNENYE S. NNEBE, JEANNE GUILLORY