Abstract: Integrated circuits, methods, and computer programs are directed to performing proof-of-work (POW) operations. One integrated circuit includes a nonce register for storing a nonce value, a first one-way function (OWF) circuit configured to generate a hash of a header, a dynamic transform circuit configured to transform the hash of the header to generate a transform value, and a second OWF circuit configured to generate a hash of the transform value to obtain a validation parameter. The header includes the nonce value for POW validation of the header. Further, the transformation by the dynamic transform circuit is based on the nonce value. The validation parameter determines whether the POW meets a predetermined target for validation of the header with the nonce value.

Abstract: A transform-enabled integrated circuit for use in cryptographic proof-of-work systems is provided. The transform-enabled integrated circuit includes a transformation block embedded among other circuitry components within the cryptographic datapath of the transform-enabled integrated circuit. The transformation block may be configured at a time subsequent to the manufacture of the integrated circuit to embody as circuitry any one of a plurality of mathematical transformation functions, thus enabling a user to systemically modify the results of cryptographic operations performed by the integrated circuit while retaining the high performance and efficiency characteristics of application specific integrated circuits.

Abstract: A transform-enabled integrated circuit is provided with a combined transformation/hashing block, such as for cryptographic proof-of-work systems. The transform-enabled integrated circuit embeds components for a transformation function among hashing function components within the cryptographic datapath of the transform-enabled integrated circuit. The combined transformation/hashing block may be configured after the manufacture of the integrated circuit to embody as circuitry any one of a plurality of mathematical transformation functions, thus enabling a user to systemically modify the cryptographic operations performed by the integrated circuit while retaining the high performance and efficiency characteristics of application specific integrated circuits. Embodiments modify the internal intermediate state variables of the hashing function to transform and hash an input message. Method and computer program product embodiments are also provided.

Abstract: Integrated circuits, methods, and computer programs are directed to performing proof-of-work (POW) operations. One integrated circuit includes a nonce register for storing a nonce value, a first one-way function (OWF) circuit configured to generate a hash of a header, a dynamic transform circuit configured to transform the hash of the header to generate a transform value, and a second OWF circuit configured to generate a hash of the transform value to obtain a validation parameter. The header includes the nonce value for POW validation of the header. Further, the transformation by the dynamic transform circuit is based on the nonce value. The validation parameter determines whether the POW meets a predetermined target for validation of the header with the nonce value.

Abstract: An apparatus, method, and system for actively controlling power in a series string load is provided. A number of conventional low-cost power supply units energize a number of voltage-regulation modules (VRMs) connected to each other in series. Each VRM generates a regulated output voltage using a pulse-wave modulated switching circuit, and provides the regulated output voltage to a number of load elements. Each VRM also sends signals to a central controller describing the output voltage applied to its connected load elements, and adjusts the output voltage applied to its connected load elements in response to signals received from the central controller. The supply voltage provided to individual load elements may thus be accurately and dynamically controlled during operation. Each load element may comprise a light-emitting device, a microprocessor, or a cryptographic integrated circuit with a plurality of processing cores. Optocouplers or load-shifters send signals across different supply voltage domains.

Abstract: An apparatus, method, and system for actively controlling supply voltage distribution and computational tasks performed by a number of processor cores in a load element of a series string load is provided. An I/O block and a local controller in a given load element manage external communications and internal data and power, respectively. The local controller tests the processor cores for functionality and error-free computation time requirements by providing test input data after various propagation delays and comparing a computed output result to a known correct result. The timing tests may be repeated at different power supply voltages. The local controller may deem processor cores non-functional, idle processor cores deemed unusually slow, and/or adjust processor core supply voltages to best dynamically manage the load element. The local controller seeks to produce most error-free computations at the highest possible speed and at the lowest overall load element power dissipation.

Abstract: A transform-enabled integrated circuit is provided with a combined transformation/hashing block, such as for cryptographic proof-of-work systems. The transform-enabled integrated circuit embeds components for a transformation function among hashing function components within the cryptographic datapath of the transform-enabled integrated circuit. The combined transformation/hashing, block may be configured after the manufacture of the integrated circuit to embody as circuitry any one of a plurality of mathematical transformation functions, thus enabling a user to systemically modify the cryptographic operations performed by the integrated circuit while retaining the high performance and efficiency characteristics of application specific integrated circuits. Embodiments modify the internal intermediate state variables of the hashing function to transform and hash an input message. Method and computer program product embodiments are also provided.

Abstract: A transform-enabled integrated circuit for use in cryptographic proof-of-work systems is provided. The transform-enabled integrated circuit includes a transformation block embedded among other circuitry components within the cryptographic datapath of the transform-enabled integrated circuit. The transformation block may be configured at a time subsequent to the manufacture of the integrated circuit to embody as circuitry any one of a plurality of mathematical transformation functions, thus enabling a user to systemically modify the results of cryptographic operations performed by the integrated circuit while retaining the high performance and efficiency characteristics of application specific integrated circuits.

Abstract: A transform-enabled integrated circuit is provided with a combined transformation/hashing block, such as for cryptographic proof-of-work systems. The transform-enabled integrated circuit embeds components for a transformation function among hashing function components within the cryptographic datapath of the transform-enabled integrated circuit. The combined transformation/hashing block may be configured after the manufacture of the integrated circuit to embody as circuitry any one of a plurality of mathematical transformation functions, thus enabling a user to systemically modify the cryptographic operations performed by the integrated circuit while retaining the high performance and efficiency characteristics of application specific integrated circuits. Embodiments modify the internal intermediate state variables of the hashing function to transform and hash an input message. Method and computer program product embodiments are also provided.

Abstract: A transform-enabled integrated circuit for use in cryptographic proof-of-work systems is provided. The transform-enabled integrated circuit includes a transformation block embedded among other circuitry components within the cryptographic datapath of the transform-enabled integrated circuit. The transformation block may be configured at a time subsequent to the manufacture of the integrated circuit to embody as circuitry any one of a plurality of mathematical transformation functions, thus enabling a user to systemically modify the results of cryptographic operations performed by the integrated circuit while retaining the high performance and efficiency characteristics of application specific integrated circuits.

Abstract: A transform-enabled integrated circuit for use in cryptographic proof-of-work systems is provided. The transform-enabled integrated circuit includes a transformation block embedded among other circuitry components within the cryptographic datapath of the transform-enabled integrated circuit. The transformation block may be configured at a time subsequent to the manufacture of the integrated circuit to embody as circuitry any one of a plurality of mathematical transformation functions, thus enabling a user to systemically modify the results of cryptographic operations performed by the integrated circuit while retaining the high performance and efficiency characteristics of application-specific integrated circuits.

Abstract: A memory is disclosed having one or more logic level reinforcement circuits (LLRC's) coupled to each wordline. Each LLRC has an input and an output, both of which are coupled to a corresponding wordline. The LLRC senses a present logic level on the wordline. If the present logic level is a first logic level, then the LLRC outputs a first logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. If the present logic level is the second logic level, then the LLRC outputs a second logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. By doing so, the LLRC compensates for the undesirable effects of gate leakage, and enables the memory to operate effectively and efficiently despite the gate leakage.

Abstract: A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.

Abstract: A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.