Abstract: Bits are stored in cells having two transistors between two parallel bitlines. In a memory array, first and second transistor channels in a bit cell are parallel and offset and coupled to first and second bitlines, respectively, which are also parallel and offset. Adjacent bit cells share corresponding transistor channel structures. The transistor channels may be orthogonal to the bitlines. The memory array may be on an integrated circuit (IC) die, which may be coupled to a power supply in an IC system. In an IC system, the memory array may be coupled to a power supply and a cooling structure.

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

Abstract: The present invention discloses a pharmaceutical composition comprising 1-{3-[9-methoxy-7-(2-methoxyphenyl)-2,3,4,5-tetrahydro-1,4-benzoxazepine-4-carbonyl]phenyl}imidazolidin-2-one; N-tert-butyl-2-{N-[(furan-2-yl)methyl]-2-[5-(4-methylphenyl)-2H-1,2,3,4-tetrazol-2-yl]acetamido}-2-(4-hydroxyphenyl)acetamide; 3-[2-(2-{[(6-hydroxy-2,4-dioxo-1,2,3,4-tetrahydropyrimidin-5-yl)(4hydroxyphenyl) methyl]amino}-4-oxo-4,5-dihydro-1,3-thiazol-5-yl) acetamido]benzoic acid; 2-oxo-2-(1H-pyrrol-2-yl)ethyl 2-[(4-fluorophenyl)methoxy]benzoate; and 5-(3-{[(3-bromo-4-hydroxy-5 methoxyphenyl) methylidene]amino}-2 (butylimino)-2,3-dihydro-1,3-thiazol-4-yl)-2-hydroxybenzamide. The components are small molecule antagonists that increase the intracellular nitric oxide level by inhibiting the interaction between Nitric oxide synthase interacting proteins and inducible Nitric oxide synthase.

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in an array; and a plurality of photonic integrated circuit (PIC) dies, each PIC die having waveguides. Adjacent microelectronic sub-assemblies are coupled to one of the PIC dies by interconnects such that any one PIC die is coupled to more than two adjacent microelectronic sub-assemblies, and the microelectronic sub-assemblies coupled to each PIC die in the plurality of PIC dies are communicatively coupled by the waveguides in the PIC die. Each microelectronic sub-assembly comprises: an interposer integrated circuit (IC) die comprising one or more electrical controller circuit proximate to at least one edge of the interposer IC die; a first plurality of IC dies coupled to a first surface of the interposer IC die; and a second plurality of IC dies coupled to an opposing second surface of the interposer IC die.

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

Abstract: Described herein are methods and compositions for treating MPS I (Hurler/Hurler-Scheie/Scheie Syndrome) by administering to the subject a composition comprising a iduronidase (IDUA) polynucleotide. In one aspect, provided is a method of reducing, delaying and/or eliminating one or more of the need for additional treatment procedures, the onset, progression and/or severity of symptoms in a subject with MPS I, by administering to the subject a composition comprising a iduronidase (IDUA) polynucleotide.

Abstract: Systems and methods are provided for identifying and rendering content relevant to a user's current mental state and context. In an aspect, a system includes a state component that determines a state of a user during a current session of the user with the media system based on navigation of the media system by the user during the current session, media items provided by the media system that are played for watching by the user during the current session, and a manner via which the user interacts with or reacts to the played media items. In an aspect, the state of the user includes a mood of the user. A selection component then selects a media item provided by the media provider based on the state of the user, and a rendering component effectuates rendering of the media item to the user during the current session.

Abstract: A device may receive radio frequency (RF) transmissions from access points provided in a zone, and may calculate channel state information (CSI) for the access points based on the RF transmissions. The device may identify CSI phases that satisfy a phase threshold to eliminate surrounding movement in the zone and to focus on an entry location of the zone, and may perform a short-time Fourier transform of the CSI phases to generate a frequency versus time graph. The device may perform a spectrogram analysis of the frequency versus time graph or may process the frequency versus time graph, with a machine learning model, to determine a quantity of people in the zone and a start and stop times associated with entries and exits of the people to and from the zone. The device may perform actions based on the quantity of people and the start and stop times.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) detects a collision between a duration in time domain configured to receive downlink data for a dedicated data subscription (DDS) subscription of the MSIM UE and a first paging occasion configured to receive a paging message for a non-DDS (n-DDS) subscription of the MSIM UE. The UE may then monitor a second paging occasion different from the first paging occasion for the paging message, the second paging occasion configured to avoid collision with the duration in time domain.

Abstract: Accelerating artificial intelligence workflows, including: receiving, from a computing process of an artificial intelligence workflow, a request for information stored on a data repository; issuing, from a user space of an operating system environment, parallel requests to the data repository using a network protocol that operates serially at the kernel level of the operating system environment; receiving, from the data repository, one or more responses to the parallel requests; and providing, to the computing process of the artificial intelligence workflow and based on the one or more responses to the parallel requests, a response to the request for information.

Abstract: In one embodiment, an apparatus comprises: a plurality of banks to store data; and a plurality of interconnects, each of the plurality of interconnects to couple a pair of the plurality of banks. In response to a data movement command, a first bank of the plurality of banks is to send data directly to a second bank of the plurality of banks via a first interconnect of the plurality of interconnects. Other embodiments are described and claimed.

Abstract: Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.

Abstract: A computer system is used to initiate a process to configure an external accessory for use with at least a first device management application. The computer system displays a prompt that includes an option to initiate a process to configure the external accessory for use with at least a first device management application. While displaying the prompt, the computer system optionally receives a selection and/or an input corresponding to a selection of an option to initiate a process to configure the external accessory for use with at least a first device management application.

Abstract: IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. Similarly, a routing track is referred to as an “angled routing track” if the routing track is neither perpendicular nor parallel to any edges of front or back faces of the support structure. Angled transistors and angled routing tracks provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

Abstract: Examples of a system and methods for quantifying patient improvement via artificial intelligence are disclosed. In general, via at least one processing element, a machine learning model such as a Siamese neural network is trained in view of a cost function to learn on average a maximum difference in outcomes between a patient at different points in time. Given the architecture of the neural network, a plurality of outcome measures generated for a given point in time can be condensed into a single score.

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.

Abstract: Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.

Abstract: IC devices with logic circuits using vertical transistors with backside source or drain (S/D) regions, and related assemblies and methods, are disclosed herein. An example vertical transistor includes an elongated structure (e.g., a nanoribbon) of one or more semiconductor materials extending between a first side (e.g., a back side) and an opposing second side (e.g., a front side) of a substrate. The first S/D region of the transistor may be provided at the first side of the substrate, while the second S/D region of the transistor may be provided at the second side, with the channel region of the transistor being the portion of the elongated structure between the first and second S/D regions. Implementing various logic circuits using vertical transistors with backside S/D regions may provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.