Abstract: A field programmable gate array (FPGA), that includes a trusted FPGA logic, an untrusted FPGA logic and a monitor; wherein the monitor is configured to monitor the untrusted FPGA logic and prevent the untrusted FPGA logic from violating predefined constrains imposed on an operation of the untrusted FPGA logic; wherein the predefined constraints are stored in a memory region of the FPGA that is not accessible to the untrusted FPGA logic.

Abstract: A method and a system for controlling the access of a plurality of client computers to storage media, the system including: a processor, a Random-Access Memory (RAM) device; and a Network Interface Controller (NIC), configured to establish a plurality of connections with the clients. The processor may dynamically allocate a buffer memory space to each connected client computer on the RAM device, and the NIC may be configured to receive at least one storage access request from at least one client, over at least one computer network connection. The RAM device may accumulate data of the at least one storage access request in the buffer allocated to the respective connected client computer, and the processor may be configured, upon completion of the accumulation of data, to propagate the buffered data to at least one storage device of the storage media.

Abstract: A storage system that includes an in-line hardware accelerator, a solid-state drive (SSD) unit, a central processing unit (CPU), a volatile memory module, and an accelerator memory module that is coupled to the in-line hardware accelerator or belongs to the in-line hardware accelerator; wherein the in-line hardware accelerator is directly coupled to the SSD unit, the volatile memory and the non-volatile memory; wherein the CPU is directly coupled to the volatile memory and to the non-volatile memory; wherein the in-line hardware accelerator is configured to manage access to the SSD unit; wherein the in-line accelerator is configured to retrieve data stored in the volatile memory module and the non-volatile memory module without involving the CPU.

Abstract: A method and a system for accelerating computer data garbage collection (GC) on a non-volatile memory (NVM) computer storage device may include: monitoring, by a processor, a data validity parameter of at least one physical write unit (PWU), where the PWU may include a plurality of physical data pages of the NVM device; sending at least one GC command from the processor to an accelerator associated with the NVM device, based on the monitored data validity parameter; copying, by the accelerator, a plurality of data-objects stored on at least one first PWU, to a read address space comprised within the accelerator; copying valid data-objects from the read address space to a write address space comprised within the accelerator until the amount of data in the write address space exceeds a predefined threshold; and storing, by the accelerator, the data content in at least one second PWU in the NVM media.

Abstract: A system and a method for reducing read latency of a storage media associated with at least one host computer, by at least one processor, may include assigning each storage segment of the non-volatile storage to a first Read-Latency Set (RLS) and a second RLS, wherein the first RLS is attributed a read/write mode and the second RLS is attributed a read-only mode; receiving read-requests and write-requests from the at least one host computer, wherein each of said requests is attributed a priority; and serving the received requests according to RLS work modes and according to the priority of each request.

Abstract: A system and method of managing non-volatile computer storage media may include: receiving at least one value of at least one parameter, including for example: a size of data objects, a frequency of data write requests, a size of write units (WUs) and a required write amplification value; setting a cyclic write pointer to point to a WU having a logical address space; setting a cyclic garbage collection (GC) pointer to point to a WU having a logical address space, located ahead of the WU pointed by the write pointer; performing GC on the WU pointed by the GC pointer; and incrementing the cyclic GC pointer to point to a next WU according to the value of the cyclic write pointer and according to the at least one received parameter value.