Abstract: In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.

Abstract: In a processing system, a method includes selecting, at a timer management component of a processor, a timer ring of a set of timer rings for a requested timer based on a time unit granularity associated with the requested timer, wherein each timer ring of the set has a different time unit granularity. The method further includes instantiating the requested timer in a selected entry of the selected timer ring. Instantiating the requested timer may include fixedly maintaining a record for the requested timer in the selected entry of the selected timer ring for the entire time span of the requested timer.

Abstract: In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.

Abstract: In a processing system, a method includes selecting, at a timer management component of a processor, a timer ring of a set of timer rings for a requested timer based on a time unit granularity associated with the requested timer, wherein each timer ring of the set has a different time unit granularity. The method further includes instantiating the requested timer in a selected entry of the selected timer ring. Instantiating the requested timer may include fixedly maintaining a record for the requested timer in the selected entry of the selected timer ring for the entire time span of the requested timer.

Abstract: A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Abstract: A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.

Abstract: A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting.

Abstract: A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Abstract: A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.

Abstract: A method for executing a DMA task, the method includes receiving a request to execute a DMA task; the method characterized by including: defining inter-buffer jumping points at substantially an end of one or more dimensions of each multidimensional buffer out of a plurality of multidimensional buffers; and executing multiple DMA sub-tasks, wherein the executing includes jumping between buffers at the inter-buffer jumping points. A device hat includes at least one memory unit and a DMA controller adapted to access the memory unit; the device is characterized by being adapted to implement multidimensional buffers within the at least one memory unit; wherein the DMA controller is adapted to execute multiple DMA sub-tasks, wherein the execution comprises jumping between buffers at inter-buffer jumping points; and wherein the inter-buffer jumping points are defined at substantially an end of one or more dimensions of each multidimensional buffer out of a plurality of multidimensional buffers.