Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

Abstract: An information processing system includes a processor for processing information; a processor bus, a first expansion bus; a host bridge for coupling the processor bus to the first expansion bus; a second expansion bus; a first bus bridge for coupling the first expansion bus to the second expansion bus; a plurality of input/output (I/O) devices coupled to the second expansion bus; and a first storage device for storing a first set of configuration data for the plurality of I/O devices; a second storage device for storing additional configuration data. The first storage device includes a register for storing a pointer for pointing to addresses in the first storage device for forwarding addresses sent from the processor to the I/O devices.

Abstract: A bridge is provided between an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus and performs memory cycles on both buses simultaneously when a master on the ISA bus initiates a memory transfer. Data is steered between the ISA and PCI buses when a slave on the PCI bus claims the memory address within a predetermined time period after the memory cycle is initiated on the PCI bus. The ISA bus is isolated from the PCI bus when no slave on the PCI bus claims the memory address. This allows the memory cycle to be completed on the ISA bus, and the memory cycle on the PCI bus is terminated.