Patents by Inventor Sagi Kuks
Sagi Kuks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210384998Abstract: A network element (36) includes circuitry and at least one port (72). The at least one port is coupled to an optical fabric (32) including one or more optical switches (40) that provide optical paths between the at least one port and multiple destination nodes, at predefined time slots. The circuitry is configured to hold a schedule plan (84) that specifies which of the destination nodes are accessible via the optical fabric at which of the time slots, to queue packets that are destined to the destination nodes, and to transmit the queued packets via the at least one port in accordance with the schedule plan.Type: ApplicationFiled: January 3, 2019Publication date: December 9, 2021Inventors: Liron Mula, Elad Mentovich, Paraskevas Bakopoulos, Eitan Zahavi, Sagi Kuks
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Patent number: 11032206Abstract: A network element includes multiple ports and logic. The multiple ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a network. The logic is configured to queue the packets received from the ingress ports, run a packet-dropping process that randomly drops one or more of the queued packets to avoid congestion, while detecting and excluding from the packet-dropping process, at least probabilistically, packets belonging to a predefined packet type, and forward the queued packets, which were not dropped, to the egress ports.Type: GrantFiled: November 6, 2018Date of Patent: June 8, 2021Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Liron Mula, Sagi Kuks
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Patent number: 10951549Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.Type: GrantFiled: March 7, 2019Date of Patent: March 16, 2021Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: George Elias, Gil Levy, Liron Mula, Aviv Kfir, Benny Koren, Sagi Kuks
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Patent number: 10938715Abstract: A network element includes output ports, a crossbar fabric and a scheduler. The output ports are organized in groups of multiple output ports selectable over predefined time slots in accordance with a cyclic mapping assigned to each group. In each time slot, the crossbar fabric routes to fabric outputs data received from the buffers via fabric inputs, in accordance with a routing plan. The scheduler determines and applies the routing plan for transmitting packets from the buffers to the communication network via the crossbar fabric and output ports. When in a given time slot, a required readout rate from a given buffer exceeds a maximum rate, the scheduler selects a group of the output ports to which the given buffer is routed in that time slot, and modifies the cyclic mapping for that group to reduce the required readout rate from the given buffer in the given time slot.Type: GrantFiled: June 11, 2019Date of Patent: March 2, 2021Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Ofir Merdler, George Elias, Yuval Shpigelman, Eyal Srebro, Sagi Kuks
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Patent number: 10880236Abstract: Communication apparatus includes multiple ports configured to serve as ingress and egress ports, such that the ingress ports receive packets from a packet data network for forwarding to respective egress ports. The ports include an egress port configured for connection to a network interface controller (NIC) serving multiple physical computing units, which have different, respective destination addresses and are connected to the NIC by different, respective communication channels. Control and queuing logic is configured to queue the packets that are received from the packet data network for forwarding to the multiple physical computing units in different, respective queues according to the destination addresses, and to arbitrate among the queues so as to convey the packets from the queues via the same egress port to the NIC, for distribution to the multiple physical computing units over the respective communication channels.Type: GrantFiled: October 18, 2018Date of Patent: December 29, 2020Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Lion Levi, Eitan Zahavi, Amiad Marelli, George Elias, Liron Mula, Oded Zemer, Sagi Kuks, Barak Gafni, Gal Shohet, Harold Rosenstock
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Publication number: 20200396158Abstract: A network element includes output ports, a crossbar fabric and a scheduler. The output ports are organized in groups of multiple output ports selectable over predefined time slots in accordance with a cyclic mapping assigned to each group. In each time slot, the crossbar fabric routes to fabric outputs data received from the buffers via fabric inputs, in accordance with a routing plan. The scheduler determines and applies the routing plan for transmitting packets from the buffers to the communication network via the crossbar fabric and output ports. When in a given time slot, a required readout rate from a given buffer exceeds a maximum rate, the scheduler selects a group of the output ports to which the given buffer is routed in that time slot, and modifies the cyclic mapping for that group to reduce the required readout rate from the given buffer in the given time slot.Type: ApplicationFiled: June 11, 2019Publication date: December 17, 2020Inventors: Ofir Merdler, George Elias, Yuval Shpigelman, Eyal Srebro, Sagi Kuks
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Publication number: 20200287846Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.Type: ApplicationFiled: March 7, 2019Publication date: September 10, 2020Inventors: George Elias, Gil Levy, Liron Mula, Aviv Kfir, Benny Koren, Sagi Kuks
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Publication number: 20200145340Abstract: A network element includes multiple ports and logic. The multiple ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a network. The logic is configured to queue the packets received from the ingress ports, run a packet-dropping process that randomly drops one or more of the queued packets to avoid congestion, while detecting and excluding from the packet-dropping process, at least probabilistically, packets belonging to a predefined packet type, and forward the queued packets, which were not dropped, to the egress ports.Type: ApplicationFiled: November 6, 2018Publication date: May 7, 2020Inventors: Liron Mula, Sagi Kuks
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Publication number: 20200127946Abstract: Communication apparatus includes multiple ports configured to serve as ingress and egress ports, such that the ingress ports receive packets from a packet data network for forwarding to respective egress ports. The ports include an egress port configured for connection to a network interface controller (NIC) serving multiple physical computing units, which have different, respective destination addresses and are connected to the NIC by different, respective communication channels. Control and queuing logic is configured to queue the packets that are received from the packet data network for forwarding to the multiple physical computing units in different, respective queues according to the destination addresses, and to arbitrate among the queues so as to convey the packets from the queues via the same egress port to the NIC, for distribution to the multiple physical computing units over the respective communication channels.Type: ApplicationFiled: October 18, 2018Publication date: April 23, 2020Inventors: Lion Levi, Eitan Zahavi, Amiad Marelli, George Elias, Liron Mula, Oded Zemer, Sagi Kuks, Barak Gafni, Gal Shohet, Harold Rosenstock
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Patent number: 10601714Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.Type: GrantFiled: April 26, 2018Date of Patent: March 24, 2020Assignee: Mellanox Technologies TLV Ltd.Inventors: Eyal Srebro, Sagi Kuks, Liron Mula, Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Niv Aibester
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Patent number: 10594617Abstract: A network device includes circuitry and multiple ports. The circuitry is configured to hold a definition of a normalization function that determines, based on (i) a reference probability of applying a congestion indication operation to packets having a predefined reference packet-size and (ii) a packet-size parameter, a normalized probability of applying the congestion indication operation to packets whose size equals the packet-size parameter. The normalization function depends exponentially on a ratio between the packet-size parameter and the reference packet-size. The circuitry id configured to store packets in a queue, and to schedule transmission of at least some of the queued packets via an output port, to calculate the normalized probability for a given packet, by applying the normalization function to an actual reference probability and an actual size of the given packet, and randomly apply a congestion indication operation to the given packet, in accordance with the normalized probability.Type: GrantFiled: September 16, 2018Date of Patent: March 17, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Alex Shpiner, Sagi Kuks, Liron Mula, Gil Levy
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Publication number: 20190089644Abstract: A network device includes circuitry and multiple ports. The circuitry is configured to hold a definition of a normalization function that determines, based on (i) a reference probability of applying a congestion indication operation to packets having a predefined reference packet-size and (ii) a packet-size parameter, a normalized probability of applying the congestion indication operation to packets whose size equals the packet-size parameter. The normalization function depends exponentially on a ratio between the packet-size parameter and the reference packet-size. The circuitry id configured to store packets in a queue, and to schedule transmission of at least some of the queued packets via an output port, to calculate the normalized probability for a given packet, by applying the normalization function to an actual reference probability and an actual size of the given packet, and randomly apply a congestion indication operation to the given packet, in accordance with the normalized probability.Type: ApplicationFiled: September 16, 2018Publication date: March 21, 2019Inventors: Alex Shpiner, Sagi Kuks, Liron Mula, Gil Levy
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Patent number: 10218642Abstract: A network switch includes circuitry and multiple ports, including multiple input ports and at least one output port, configured to connect to a communication network. The circuitry includes multiple distinct-flow counters, which are each associated with a respective input port and with the output port, and which are configured to estimate respective distinct-flow counts of distinct data flows received via the respective input ports and destined to the output port. The circuitry is configured to store packets that are destined to the output port and were received via the multiple input ports in multiple queues, to determine a transmission schedule for the packets stored in the queues, based on the estimated distinct-flow counts, and to transmit the packets via the output port in accordance with the determined transmission schedule.Type: GrantFiled: March 27, 2017Date of Patent: February 26, 2019Assignee: Mellanox Technologies TLV Ltd.Inventors: Liron Mula, Sagi Kuks, George Elias, Eyal Srebro, Ofir Merdler, Amiad Marelli, Lion Levi, Oded Zemer, Yoav Benros
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Publication number: 20180278549Abstract: A network switch includes circuitry and multiple ports, including multiple input ports and at least one output port, configured to connect to a communication network. The circuitry includes multiple distinct-flow counters, which are each associated with a respective input port and with the output port, and which are configured to estimate respective distinct-flow counts of distinct data flows received via the respective input ports and destined to the output port. The circuitry is configured to store packets that are destined to the output port and were received via the multiple input ports in multiple queues, to determine a transmission schedule for the packets stored in the queues, based on the estimated distinct-flow counts, and to transmit the packets via the output port in accordance with the determined transmission schedule.Type: ApplicationFiled: March 27, 2017Publication date: September 27, 2018Inventors: Liron Mula, Sagi Kuks, George Elias, Eyal Srebro, Ofir Merdler, Amiad Marelli, Lion Levi, Oded Zemer, Yoav Benros
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Publication number: 20180241677Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.Type: ApplicationFiled: April 26, 2018Publication date: August 23, 2018Inventors: Eyal Srebro, Sagi Kuks, Liron Mula, Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Niv Aibester
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Patent number: 9985910Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is zero are assigned to a first group, while the flows for which the respective number is non-zero are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.Type: GrantFiled: June 28, 2016Date of Patent: May 29, 2018Assignee: Mellanox Technologies TLV Ltd.Inventors: Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Eyal Srebro, Sagi Kuks, Niv Aibester
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Publication number: 20170373989Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is zero are assigned to a first group, while the flows for which the respective number is non-zero are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.Type: ApplicationFiled: June 28, 2016Publication date: December 28, 2017Inventors: Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Eyal Srebro, Sagi Kuks, Niv Aibester