Patents by Inventor Sagi Lahav
Sagi Lahav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941428Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.Type: GrantFiled: March 31, 2022Date of Patent: March 26, 2024Assignee: Apple Inc.Inventors: Sagi Lahav, Lital Levy-Rubin, Gaurav Garg, Gerard R. Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion
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Publication number: 20240085968Abstract: A system for a given device may include a plurality of systems on a chip (SOCs). Each SOC may include an interface circuit and a bridge circuit for communicating with other SOCs. The interface circuit of an SOC may include a plurality of communication devices to transfer data packets from/to the SOC to the other SOCs. The bridge circuit may provide various control functions for the interface circuit. An indication may be generated when the system enters an idle mode. In response, the bridge circuit may generate signal(s) to cause some of the communication devices of the interface circuit into a low power state. The interface circuit may obtain the signal(s) and accordingly transition some of the communication devices to the low power state.Type: ApplicationFiled: February 28, 2023Publication date: March 14, 2024Applicant: Apple Inc.Inventors: Tzach Zemer, Lior Zimet, Sagi Lahav
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Patent number: 11836107Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.Type: GrantFiled: March 1, 2022Date of Patent: December 5, 2023Assignee: APPLE INC.Inventors: Doron Rajwan, Lior Zimet, Sagi Lahav
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Publication number: 20230350828Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.Type: ApplicationFiled: April 28, 2023Publication date: November 2, 2023Inventors: Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan M. Redshaw, Per H. Hammarlund, Eran Tamari, James Vash, Gaurav Garg, Lior Zimet, Harshavardhan Kaushikkar, Steven Fishwick, Steven R. Hutsell, Shawn M. Fukami
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Patent number: 11803471Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.Type: GrantFiled: August 22, 2022Date of Patent: October 31, 2023Assignee: Apple Inc.Inventors: Per H. Hammarlund, Lior Zimet, Sergio Kolor, Sagi Lahav, James Vash, Gaurav Garg, Tal Kuzi, Jeffry E. Gonion, Charles E. Tucker, Lital Levy-Rubin, Dany Davidov, Steven Fishwick, Nir Leshem, Mark Pilip, Gerard R. Williams, III, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan
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Publication number: 20230334003Abstract: In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.Type: ApplicationFiled: April 24, 2023Publication date: October 19, 2023Inventors: Igor Tolchinsky, Charles J. Fleckenstein, Sagi Lahav, Lital Levy-Rubin
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Publication number: 20230281154Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.Type: ApplicationFiled: March 1, 2022Publication date: September 7, 2023Inventors: Doron Rajwan, Lior Zimet, Sagi Lahav
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Patent number: 11675722Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.Type: GrantFiled: June 3, 2021Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan M. Redshaw, Per H. Hammarlund, Eran Tamari, James Vash, Gaurav Garg, Lior Zimet, Harshavardhan Kaushikkar, Steven Fishwick, Steven R. Hutsell, Shawn M. Fukami
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Patent number: 11669480Abstract: In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.Type: GrantFiled: May 13, 2021Date of Patent: June 6, 2023Assignee: Apple Inc.Inventors: Igor Tolchinsky, Charles J. Fleckenstein, Sagi Lahav, Lital Levy-Rubin
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Publication number: 20230063676Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.Type: ApplicationFiled: March 31, 2022Publication date: March 2, 2023Inventors: Sagi Lahav, Lital Levy - Rubin, Gaurav Garg, Gerard R. Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion
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Publication number: 20230064526Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.Type: ApplicationFiled: March 31, 2022Publication date: March 2, 2023Inventors: Sagi Lahav, Lital Levy - Rubin, Gaurav Garg, Gerard R. Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion
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Publication number: 20230058989Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.Type: ApplicationFiled: August 22, 2022Publication date: February 23, 2023Inventors: Per H. Hammarlund, Lior Zimet, Sergio Kolor, Sagi Lahav, James Vash, Gaurav Garg, Tal Kuzi, Jeffry E. Gonion, Charles E. Tucker, Lital Levy-Rubin, Dany Davidov, Steven Fishwick, Nir Leshem, Mark Pilip, Gerard R. Williams, III, Harshavardhan Kaushikkar, Srinivasan Rangan Sridharan
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Publication number: 20230053530Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.Type: ApplicationFiled: August 22, 2022Publication date: February 23, 2023Inventors: Per H. Hammarlund, Eran Tamari, Lior Zimet, Sergio Kolor, Sergio V. Tota, Sagi Lahav, James Vash, Gaurav Garg, Jonathan M. Redshaw, Steven R. Hutsell, Harshavardhan Kaushikkar, Shawn M. Fukami
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Patent number: 11550716Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.Type: GrantFiled: January 14, 2022Date of Patent: January 10, 2023Assignee: Apple Inc.Inventors: Gaurav Garg, Sagi Lahav, Lital Levy-Rubin, Gerard Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion, James Vash
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Publication number: 20220365896Abstract: In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Inventors: Igor Tolchinsky, Charles J. Fleckenstein, Sagi Lahav, Lital Levy-Rubin
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Publication number: 20220334997Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.Type: ApplicationFiled: June 3, 2021Publication date: October 20, 2022Inventors: Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan M. Redshaw, Per H. Hammarlund, Eran Tamari, James Vash, Gaurav Garg
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Publication number: 20220318136Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.Type: ApplicationFiled: January 14, 2022Publication date: October 6, 2022Inventors: Gaurav Garg, Sagi Lahav, Lital Levy - Rubin, Gerard Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion, James Vash
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Publication number: 20140189328Abstract: A computer processor, a computer system and a corresponding method involve a reservation station that stores instructions which are not ready for execution. The reservation station includes a storage area that is divided into bundles of entries. Each bundle is switchable between an open state in which instructions can be written into the bundle and a closed state in which instructions cannot be written into the bundle. A controller selects which bundles are open based on occupancy levels of the bundles.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Inventors: Tomer WEINER, Zeev SPERBER, Sagi LAHAV, Guy PATKIN, Gavri BERGER, Itamar FELDMAN, Ofer LEVY, Sara YAKOEL, Adi YOAZ
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Patent number: 7958336Abstract: A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.Type: GrantFiled: June 30, 2008Date of Patent: June 7, 2011Assignee: Intel CorporationInventors: Sagi Lahav, Guy Patkin, Zeev Sperber, Herbert Hum, Shih-Lien Lu, Srikanth T. Srinivasan
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Publication number: 20090327657Abstract: A processor to perform an out-of-order (OOO) processing in which a reservation station (RS) may generate and process a dependency controlled flow comprising multiple micro-operations (uops) with specific clock based dispatch scheme. The RS may either combine two or more uops into a single RS entry or make a direct connection between two or more RS entries. The RS may allow more than two source values to be associated with a single RS by combining sources from the two or more uops. One or more execution units may be provisioned to perform the function defined by the uops. The execution units may receive more than two sources at a given time point and produce two or more results on different ports.Type: ApplicationFiled: June 25, 2008Publication date: December 31, 2009Inventors: Zeev Sperber, Sagi Lahav, Guy Patkin, Simon Rubanovich, Amit Gradstein, Yuval Bustan