Patents by Inventor Sah Sudhakar

Sah Sudhakar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9880822
    Abstract: Systems and methods for use in parallelization of computer program code are provided. One method includes determining line dependency data indicating a dependency of a plurality of lines of the sequential computer program code. The method further includes determining time data indicating a time required for the execution of a plurality of functions of the sequential computer program code and determining parallelizability of the sequential computer program code using the line dependency data and the time data. The method further includes generating parallel executable computer program code by inserting program instructions in the sequential computer program code based on the determined parallelizability. The step of generating the parallel executable computer program code includes identifying and routing at least a portion of one or more of the plurality of functions to different processors to achieve parallelization of sequential computer program code using the line data and time dependency data.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: January 30, 2018
    Assignee: KPIT TECHNOLOGIES LIMITED
    Inventors: Vinay Govind Vaidya, Ranadive Priti, Sah Sudhakar
  • Publication number: 20150317140
    Abstract: Systems and methods for use in parallelization of computer program code are provided. One method includes determining line dependency data indicating a dependency of a plurality of lines of the sequential computer program code. The method further includes determining time data indicating a time required for the execution of a plurality of functions of the sequential computer program code and determining parallelizability of the sequential computer program code using the line dependency data and the time data. The method further includes generating parallel executable computer program code by inserting program instructions in the sequential computer program code based on the determined parallelizability. The step of generating the parallel executable computer program code includes identifying and routing at least a portion of one or more of the plurality of functions to different processors to achieve parallelization of sequential computer program code using the line data and time dependency data.
    Type: Application
    Filed: January 27, 2015
    Publication date: November 5, 2015
    Inventors: Vinay Govind Vaidya, Ranadive Priti, Sah Sudhakar
  • Patent number: 8949786
    Abstract: A method and system for parallelization of sequential computer program code are described. In one embodiment, an automatic parallelization system includes a syntactic analyzer to analyze the structure of the sequential computer program code to identify the positions to insert SPI to the sequential computer code; a profiler for profiling the sequential computer program code by preparing call graph to determine dependency of each line of the sequential computer program code and the time required for the execution of each function of the sequential computer program code; an analyzer to determine parallelizability of the sequential computer program code from the information obtained by analyzing and profiling of the sequential computer program code; and a code generator to insert SPI to the sequential computer program code upon determination of parallelizability to obtain parallel computer program code, which is further outputted to a parallel computing environment for execution and the method thereof.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: February 3, 2015
    Assignee: KPIT Technologies Limited
    Inventors: Vinay G. Vaidya, Ranadive Priti, Sah Sudhakar
  • Patent number: 8732714
    Abstract: A method of reorganizing a plurality of task for optimization of resources and execution time in an environment is described. In one embodiment, the method includes mapping of each task to obtain qualitative and quantitative assessment of each functional elements and variables within the time frame for execution of each tasks, representation of data obtained from the mapping in terms of a matrix of dimensions N×N, wherein N represents total number of tasks and reorganizing the tasks in accordance with the represented data in the matrix for the execution, wherein reorganizing the tasks provides for both static and dynamic methodologies. It is advantageous that the present invention determines optimal number of resources required to achieve a practical overall task completion time and can be adaptable to non computer applications.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: May 20, 2014
    Assignee: Kpit Technologies Limited
    Inventors: Vinay Govind Vaidya, Ranadive Priti, Sah Sudhakar, Vipradas Jaydeep
  • Publication number: 20110246998
    Abstract: A method of reorganizing a plurality of task for optimization of resources and execution time in an environment is described. In one embodiment, the method includes mapping of each task to obtain qualitative and quantitative assessment of each functional elements and variables within the time frame for execution of each tasks, representation of data obtained from the mapping in terms of a matrix of dimensions N×N, wherein N represents total number of tasks and reorganizing the tasks in accordance with the represented data in the matrix for the execution, wherein reorganizing the tasks provides for both static and dynamic methodologies. It is advantageous that the present invention determines optimal number of resources required to achieve a practical overall task completion time and can be adaptable to non computer applications.
    Type: Application
    Filed: December 3, 2009
    Publication date: October 6, 2011
    Inventors: Vinay Govind Vaidya, Ranadive Priti, Sah Sudhakar, Vipradas Jaydeep
  • Publication number: 20110239201
    Abstract: A method and system for parallelization of sequential computer program code are described. In one embodiment, an automatic parallelization system includes a syntactic analyser to analyze the structure of the sequential computer program code to identify the positions to insert SPI to the sequential computer code; a profiler for profiling the sequential computer program code by preparing call graph to determine dependency of each line of the sequential computer program code and the time required for the execution of each function of the sequential computer program code; an analyzer to determine parallelizability of the sequential computer program code from the information obtained by analysing and profiling of the sequential computer program code; and a code generator to insert SPI to the sequential computer program code upon determination of parallelizability to obtain parallel computer program code, which is further outputted to a parallel computing environment for execution and the method thereof.
    Type: Application
    Filed: December 1, 2009
    Publication date: September 29, 2011
    Inventors: Vinay G. Vaidya, Ranadive Priti, Sah Sudhakar