Patents by Inventor Sahana Sriraj

Sahana Sriraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CURRENT LIMITER CIRCUIT WITH ADJUSTABLE RESPONSE TIME
    Publication number: 20240113517
    Abstract: A current limiter includes a gain adjustment circuit designed to change the response time (e.g., operation mode) of the current limiter. The current limiter may be designed to operate at different selectable speed modes (e.g., slow mode, fast mode) that affect how quickly the current limiter responds to an overcurrent stimulus. The speed modes may be selected by choosing between different current mirror arrangements in the gain adjustment circuit. Regardless of which mode of operation is selected for the current limiter, a speedup circuit may also be implemented, which includes a switch to initiate a nonlinear speedup of the response time after a certain overcurrent stimulus is received.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Sahana Sriraj, Ralph Braxton Wade, III
  • Method and circuitry for compensating low dropout regulators
    Patent number: 11009900
    Abstract: Low dropout regulators (LDOs) are disclosed herein. An example of an LDO includes an error amplifier having a first input and a second input, wherein the first input is for coupling to an output of the LDO and the second input for coupling to a reference voltage. The error amplifier has an output with a voltage that is proportional to the difference between the output voltage and the reference voltage. A second amplifier is coupled between the error amplifier and the output of the LDO. A gain boost amplifier is coupled between the error amplifier and the second amplifier. The gain boost amplifier increases DC gain of the LDO in response to a load step on the output.
    Type: Grant
    Filed: January 7, 2017
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim Valerievich Ivanov, Sahana Sriraj
  • METHOD AND CIRCUITRY FOR COMPENSATING LOW DROPOUT REGULATORS
    Publication number: 20180196454
    Abstract: Low dropout regulators (LDOs) are disclosed herein. An example of an LDO includes an error amplifier having a first input and a second input, wherein the first input is for coupling to an output of the LDO and the second input for coupling to a reference voltage. The error amplifier has an output with a voltage that is proportional to the difference between the output voltage and the reference voltage. A second amplifier is coupled between the error amplifier and the output of the LDO. A gain boost amplifier is coupled between the error amplifier and the second amplifier. The gain boost amplifier increases DC gain of the LDO in response to a load step on the output.
    Type: Application
    Filed: January 7, 2017
    Publication date: July 12, 2018
    Inventors: Vadim Valerievich Ivanov, Sahana Sriraj