Patents by Inventor Sahar Khalili

Sahar Khalili has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947995
    Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kuan Hua Tan, Sahar Khalili, Eng Hun Ooi, Shrinivas Venkatraman, Dimpesh Patel
  • Patent number: 11036412
    Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Sahar Khalili, Zvika Greenfield, Sowmiya Jayachandran, Robert J. Royer, Jr., Dimpesh Patel
  • Publication number: 20210097004
    Abstract: A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 1, 2021
    Inventors: Suresh NAGARAJAN, Scott CRIPPIN, Sahar KHALILI, Shankar NATARAJAN, Romesh TRIVEDI
  • Patent number: 10942672
    Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Shrinivas Venkatraman, Eng Hun Ooi, Sahar Khalili, Dimpesh Patel, Kuan Hua Tan
  • Publication number: 20200278883
    Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Kuan Hua TAN, Sahar KHALILI, Eng Hun OOI, Shrinivas VENKATRAMAN, Dimpesh PATEL
  • Publication number: 20200034061
    Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 30, 2020
    Inventors: Sahar KHALILI, Zvika GREENFIELD, Sowmiya JAYACHANDRAN, Robert J. ROYER, JR., Dimpesh PATEL
  • Publication number: 20190278513
    Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Shrinivas Venkatraman, Eng Hun Ooi, Sahar Khalili, Dimpesh Patel, Kuan Hua Tan
  • Publication number: 20190042155
    Abstract: Systems, apparatuses and methods may provide for technology to add non-address metadata to a memory address field of a transaction layer packet (TLP), wherein the non-address metadata includes one or more vendor-specific attributes. Additionally, the technology may coordinate between a transmitter and a receiver to prevent the TLP from violating an address boundary constraint associated with an interface. In one example, the address boundary constraint prohibits an address and length combination of the TLP from crossing a 4-KB boundary.
    Type: Application
    Filed: May 14, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Eng Hun Ooi, Shrinivas Venkatraman, Kuan Hua Tan, Ang Li, Sahar Khalili, Su Wei Lim, Robert Royer, JR.