Patents by Inventor Sahilpreet Singh
Sahilpreet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9349437Abstract: A memory cell having integrated read and write assist functionality includes a storage element and first and second switching circuits. The first switching circuit is configured to selectively couple a first internal storage node of the storage element with a first bit line. The second switching circuit is configured to selectively couple a second internal storage node of the storage element with a second bit line. During a read operation, at least one of the first and second switching circuits is configured to increase a switching threshold of at least one inverter in the storage element. During a write operation, at least one of the first and second switching circuits is configured such that ground bounce associated with at least one of the first and second switching circuits assists in writing a logical state of the memory cell.Type: GrantFiled: May 16, 2014Date of Patent: May 24, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Sahilpreet Singh, Anjana Das
-
Publication number: 20150332755Abstract: A memory cell having integrated read and write assist functionality includes a storage element and first and second switching circuits. The first switching circuit is configured to selectively couple a first internal storage node of the storage element with a first bit line. The second switching circuit is configured to selectively couple a second internal storage node of the storage element with a second bit line. During a read operation, at least one of the first and second switching circuits is configured to increase a switching threshold of at least one inverter in the storage element. During a write operation, at least one of the first and second switching circuits is configured such that ground bounce associated with at least one of the first and second switching circuits assists in writing a logical state of the memory cell.Type: ApplicationFiled: May 16, 2014Publication date: November 19, 2015Applicant: LSI CorporationInventors: Sahilpreet Singh, Anjana Das
-
Patent number: 9064583Abstract: A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.Type: GrantFiled: February 25, 2013Date of Patent: June 23, 2015Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Rajiv Kumar Roy, Disha Singh, Sahilpreet Singh
-
Publication number: 20150043270Abstract: A memory cell includes a storage element including a pair of cross-coupled inverters, and first switching circuitry for selectively connecting at least one internal storage node of the storage element with a corresponding bit line as a function of a first control signal. Write assist circuitry is connected between a supply node of a device of at least one of the cross-coupled inverters and a voltage supply of the memory cell, and second switching circuitry selectively couples the supply node of the device of at least one of the cross-coupled inverters with the corresponding bit line as a function of a second control signal. During a write operation, the write assist circuitry disconnects the storage element from the voltage supply, and the second circuitry connects the supply node of the device of at least one of the cross-coupled inverters with the corresponding bit line.Type: ApplicationFiled: March 27, 2014Publication date: February 12, 2015Applicant: LSI CORPORATIONInventors: Sahilpreet Singh, Anjana Das
-
Patent number: 8848474Abstract: A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node coupled to a second bitline through a second capacitor, a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor, a first transmission gate switch coupled between the first input node and the second input node, a second transmission gate switch coupled between a first common node of the first and second inverters and a second common node of the first and second inverters. The sense amplifier is maintained at a maximum gain point in a read cycle.Type: GrantFiled: January 22, 2013Date of Patent: September 30, 2014Assignee: LSI CorporationInventor: Sahilpreet Singh
-
Publication number: 20140241061Abstract: A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Applicant: LSI CorporationInventors: Rajiv Kumar Roy, Disha Singh, Sahilpreet Singh
-
Patent number: 8792293Abstract: Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.Type: GrantFiled: October 26, 2012Date of Patent: July 29, 2014Assignee: LSI CorporationInventors: Sahilpreet Singh, Disha Singh
-
Publication number: 20140204659Abstract: A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node coupled to a second bitline through a second capacitor, a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor, a first transmission gate switch coupled between the first input node and the second input node, a second transmission gate switch coupled between a first common node of the first and second inverters and a second common node of the first and second inverters. The sense amplifier is maintained at a maximum gain point in a read cycle.Type: ApplicationFiled: January 22, 2013Publication date: July 24, 2014Applicant: LSI CorporationInventor: Sahilpreet Singh
-
Publication number: 20140192603Abstract: Described embodiments provide a memory having at least one sense amplifier with inputs coupled to at least one pair of bit lines. One of the pair of bit lines is precharged to a power supply voltage and a second one of the pair is precharged to ground. A first switch DC-couples the first one of the pair of bit lines to a first input of a cross-coupled amplifier. A first capacitor AC-couples the second one of the pair of bit lines to a second input of the cross-coupled amplifier. Then a memory cell coupled between the first and second one of the pair of bit lines is enabled. A switch then decouples the first input from the bit line, a second capacitor is used to inject a charge of current into the first input of the cross-coupled amplifier, and then the cross-coupled amplifier is enabled.Type: ApplicationFiled: January 8, 2013Publication date: July 10, 2014Applicant: LSI CORPORATIONInventor: Sahilpreet Singh
-
Publication number: 20140119093Abstract: Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: LSI CORPORATIONInventors: Sahilpreet Singh, Disha Singh