Patents by Inventor Sahng Kyoo Lee
Sahng Kyoo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7842606Abstract: Disclosed herein are a method of depositing a thin film and a method of manufacturing a semiconductor using the same, having high selectivity by increasing etching resistance while an extinction coefficient associated with anti-reflectivity is maintained low. The method of depositing a thin film according to the invention includes (a) depositing an carbon anti-reflective film on the bottom film of a substrate; and (b) adding a compound containing nitrogen (N), fluorine (F) or silicon (Si) to the surface or the inner portion of the carbon anti-reflective film, to deposit a thin film of a-C:N, a-C:F or a-C:Si, having high selectivity, to a thickness from 1 to 100 nm using an atomic layer deposition process. Therefore, an ultrathin film having etching resistance is formed on or in the carbon anti-reflective film and the density and compressive stress of the carbon anti-reflective film are increased, thus increasing etching selectivity.Type: GrantFiled: November 28, 2005Date of Patent: November 30, 2010Assignee: Integrated Process Systems LtdInventors: Ki Hoon Lee, Young Hoon Park, Sahng Kyoo Lee, Tae Wook Seo, Ho Seung Chang
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Patent number: 7785664Abstract: A method is provided for depositing thin films in which the thin films are continuously deposited into one chamber and 1-6 wafers are loaded into the chamber. In the method, a process gap between a shower head or a gas injection unit and a substrate is capable of being controlled. The method comprises (a) loading at least one substrate into the chamber, (b) depositing the Ti thin film onto the substrate, adjusted so that a first process gap is maintained, (c) moving a wafer block so that the first process gap is changed into a second process gap in order to control the process gap of the substrate upon which the Ti thin film is deposited, (d) depositing the TiN thin film onto the substrate, moved to set the second process gap, and (e) unloading the substrate upon which the Ti/TiN thin films are deposited.Type: GrantFiled: December 14, 2005Date of Patent: August 31, 2010Assignee: IPS Ltd.Inventors: Tae Wook Seo, Young Hoon Park, Ki Hoon Lee, Sahng Kyoo Lee
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Publication number: 20080166887Abstract: Disclosed herein are a method of depositing a thin film and a method of manufacturing a semiconductor using the same, having high selectivity by increasing etching resistance while an extinction coefficient associated with anti-reflectivity is maintained low. The method of depositing a thin film according to the invention includes (a) depositing an carbon anti-reflective film on the bottom film of a substrate; and (b) adding a compound containing nitrogen (N), fluorine (F) or silicon (Si) to the surface or the inner portion of the carbon anti-reflective film, to deposit a thin film of a-C:N, a-C:F or a-C:Si, having high selectivity, to a thickness from 1 to 100 nm using an atomic layer deposition process. Therefore, an ultrathin film having etching resistance is formed on or in the carbon anti-reflective film and the density and compressive stress of the carbon anti-reflective film are increased, thus increasing etching selectivity.Type: ApplicationFiled: November 28, 2005Publication date: July 10, 2008Applicant: INTEGRATED PROCESS SYSTEMS LTDInventors: Ki Hoon Lee, Young Hoon Park, Sahng Kyoo Lee, Tae Wook Seo, Ho Seung Chang
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Publication number: 20070193515Abstract: Provided is an apparatus for generating remote plasma. The apparatus includes an RF antenna disposed in regard to a chamber, a plasma generating unit formed in an uppermost portion of the chamber, wherein a plurality of plasma generation gas introduction pipes are communicated with the plasma generating unit, a first shower head disposed below the plasma generating unit, and having a plurality of first plasma guide holes, a second shower head disposed below the first shower head, and having a plurality of source/purge gas guide holes and a plurality of second plasma guide holes directly connected to the respective first plasma guide holes, and a source/purge gas introduction unit disposed between the first and second shower heads, wherein a plurality of source/purge gas introduction pipes are uniformly communicated with the source/purge gas introduction unit.Type: ApplicationFiled: February 7, 2007Publication date: August 23, 2007Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Hyeong-Tag Jeon, In-Hoe Kim, Seok-Hoon Kim, Chin-Wook Chung, Sahng-Kyoo Lee
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Patent number: 7253101Abstract: Provided is a method of depositing a metal nitride film having a multilayer structure and different deposition speeds on a substrate. The method is performed by forming a first lower metal nitride film on the substrate at a first deposition speed, forming a second lower metal nitride film on the first lower metal nitride film at a second deposition speed, and forming an upper metal nitride film having a large content of nitrogen (N) on a lower TiN film which is formed by the forming of the first lower metal nitride film and the second lower metal nitride film, at a third deposition speed, to improve stability with respect to exposure to air/moisture. The deposition speed of the metal nitride film having a multi-layer structure satisfies a relationship that the second deposition speed?the first deposition speed?the third deposition speed.Type: GrantFiled: August 17, 2005Date of Patent: August 7, 2007Assignee: IPS Ltd.Inventors: Young Hoon Park, Sahng Kyoo Lee, Tae Wook Seo
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Patent number: 6261911Abstract: The present invention relates to a method of manufacturing a junction in a semiconductor device. When forming an elevated source/drain junction (ESD) of a buried channel field effect transistor (BC-FET) using a selective epitaxial growth (SEG) technique, a self-aligned epitaxial silicon (SESS) is formed on the lower portion of a gate side-wall spacer, resulting in the improvement of a short channel characteristic by suppressing a facet occurred when forming an elevated source/drain junction (EDS) of the buried channel field effect transistors (BC-FETs) using a selective epitaxial growth (SEG) technique as well as the increase of the current density by lowering the series resistance of source/drain extension.Type: GrantFiled: February 11, 2000Date of Patent: July 17, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Jung Ho Lee, Seung Chul Lee, Noh Yeal Kwak, In Seok Yeo, Sahng Kyoo Lee
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Patent number: 6255206Abstract: A method of forming a gate electrode with a titanium polycide structure which can prevent abnormal oxidation of the gate electrode and reduce the resistivity of the gate electrode when performing a re-oxidation process, is disclosed. According to the present invention, a gate oxide layer, a polysilicon layer and a titanium silicide layer are formed on a semiconductor substrate, in sequence. A mask insulating layer is then formed in the shape of a gate electrode on the titanium silicide layer and the titanium silicide layer and the polysilicon layer are etched using the mask insulating layer to form a gate electrode. Thereafter, the substrate is oxidized using re-oxidation process to form an oxide layer with a uniform thickness on the side wall of the gate electrode and on the surface of the substrate. Here, the re-oxidation process is performed at the temperature of 750° C. or less using dry oxidation. Furthermore, the re-oxidation process is performed at the temperature of 700 to 750° C.Type: GrantFiled: November 5, 1999Date of Patent: July 3, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Se Aug Jang, Tae Kyun Kim, In Seok Yeo, Sahng Kyoo Lee
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Patent number: 5953622Abstract: A method for fabricating silicon-on-insulator (SOI) wafers which is capable of simplifying the fabrication process while improving the productivity of SOI wafers. In accordance with this method, a first wafer formed with a thermal oxide film is bonded to a second wafer formed with an oxygen ion-implanted region and a hydrogen ion-implanted region. The bonded wafer structure is annealed and then cut along the hydrogen ion-implanted region, so that it is divided into two wafer structures. The wafer structure including the first wafer is annealed to obtain a strengthened chemical coupling property. The wafer structure including the second wafer is annealed to oxidize the oxygen ion-implanted region of the second wafer, thereby forming an oxide film in the second wafer. The first and second wafers are then planarized, thereby forming a pair of SOI wafers.Type: GrantFiled: September 15, 1997Date of Patent: September 14, 1999Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sahng Kyoo Lee, Sang Kyun Park
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Patent number: 5880039Abstract: A method for forming an interlayer insulating film of semiconductor device is disclosed. A first interlayer insulating film is deposited on the entire top surface of a semiconductor device comprising a high step cell area and lower step periphery area, followed by the thermal treatment thereof. A second interlayer insulating film which is more resistant to etch than the first interlayer insulating film is deposited. Again, a third interlayer insulating film is deposited over the second interlayer insulating film, followed by the heat treatment thereof. These interlayer insulating films are planarized by a CMP process. Upon the CMP process, the first interlayer insulating film is rapidly etched out while the second interlayer insulating film is slowly removed and this difference in etching rate allows the polishing end point to be readily detected without an additional detector.Type: GrantFiled: May 1, 1997Date of Patent: March 9, 1999Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Sahng Kyoo Lee
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Patent number: 5707686Abstract: A method for preventing moisture from being absorbed into an impurity-contained insulating layer is disclosed, including the steps of: forming an impurity-contained insulating layer on a substrate; and coating a material of an alcohol group on the impurity-contained insulating layer, to form an alcohol film.Type: GrantFiled: October 31, 1995Date of Patent: January 13, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Sahng Kyoo Lee