Abstract: A semiconductor device includes a channel on a substrate, the channel including a two-dimensional (2D) material, a gate insulating layer on a portion of the channel, a gate electrode on the gate insulating layer, first and second contact patterns on respective portions of the channel, the first and second contact patterns including a carbide of a transition metal, and first and second source/drain electrodes on the first and second contact patterns, respectively, and the first and second source/drain electrodes including a metal.

Abstract: A semiconductor device includes an active region on a substrate, a gate structure on the substrate and intersecting the active region, a source/drain region on the active region on both sides of the gate structure and including silicon (Si), and a contact structure on the source/drain region. The source/drain region includes a shallow doping region doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region. A concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to an upper surface of the substrate.

Abstract: A semiconductor device includes a channel on a substrate. The channel includes a 2-dimensional material. A gate insulating layer is on a first portion of the channel. A gate electrode is on a portion of the gate insulating layer. First and second contact patterns are on second portions of the channel, respectively. Each of the first and second contact patterns includes a 2-dimensional material having an intercalation material disposed therein. First and second source/drain electrodes are on the first and second contact patterns, respectively. Each of the first and second source/drain electrodes includes a metal.

Abstract: A semiconductor device includes an active region on a substrate, a gate structure on the substrate and intersecting the active region, a source/drain region on the active region on both sides of the gate structure and including silicon (Si), and a contact structure on the source/drain region. The source/drain region includes a shallow doping region doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region. A concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to an upper surface of the substrate.

Abstract: A semiconductor device includes a plurality of semiconductor patterns stacked to be spaced apart from each other in a first direction, perpendicular to an upper surface of a substrate, and extending in a second direction, parallel to the upper surface of the substrate, a plurality of first conductive patterns extending in a third direction, perpendicular to the first direction and the second direction, on the plurality of semiconductor patterns, a plurality of second conductive patterns extending in the first direction on the substrate, a plurality of capacitors electrically connected to the plurality of semiconductor patterns, respectively, and at least one epitaxial layer disposed to be in contact with at least one of both end surfaces of at least one of the plurality of semiconductor patterns and including an impurity.

Abstract: A pattern formation method includes forming a first capping layer on a substrate, forming a recess that penetrates the first capping layer and an upper portion of the substrate, such that a non-penetrated portion of the first capping layer constitutes a first capping pattern, forming a second capping pattern that covers an inner sidewall of the recess, and forming a stack structure in the recess, such that the stack structure includes first stack patterns and second stack patterns that are alternately stacked, and the second capping pattern is between the substrate and a lateral surface of the stack structure.

Abstract: An integrated circuit device includes: an active region extending in a first horizontal direction on a substrate; a first transistor at a first vertical level on the active region, the first transistor including a first source/drain region having a first conductive type; and a second transistor at a second vertical level that is higher than the first vertical level on the active region, the second transistor including a second source/drain region having a second conductive type and overlapping the first source/drain region in a vertical direction, wherein the first source/drain region and the second source/drain region have different sizes.

Abstract: A semiconductor device includes an active region on a substrate, a gate structure on the substrate and intersecting the active region, a source/drain region on the active region on both sides of the gate structure and including silicon (Si), and a contact structure on the source/drain region. The source/drain region includes a shallow doping region doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region. A concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to an upper surface of the substrate.

Abstract: A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.

Abstract: A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.

Abstract: A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.

Abstract: A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.