Abstract: A wireless device configured for simultaneous voice and data communications is described. The wireless device includes a voice and data transceiver. The voice and data transceiver includes data path circuitry, voice path circuitry, a first multiplexer and a second multiplexer. The first multiplexer sends a primary data receive signal to the data path circuitry and receives a data transmit signal from the data path circuitry. The second multiplexer sends a diversity data receive signal to the data path circuitry, sends a voice receive signal to the voice path circuitry and receives a voice transmit signal from the voice path circuitry. The wireless device also includes a first antenna coupled to the first multiplexer. The wireless device further includes a second antenna coupled to the second multiplexer.

Abstract: Various aspects of the present disclosure are directed to apparatuses and methods that can mitigate the undesirable effects of residual side band (RSB) signal by actively re-tuning the local oscillator of a transmitter to be at or near the center frequency of the carrier. Other aspects, embodiments, and features are also claimed and described.

Abstract: An integrated circuit for achieving power reduction in a transceiver may include a jammer detector that determines an interference level corresponding to a received signal, and a transmit power detector that determines a required transmit power level for a transmitted signal. The integrated circuit may also include at least one of the following: a process monitor that determines process corners of components within the receiver and/or the transmitter, and a temperature monitor that determines a temperature of the receiver and/or the transmitter. The integrated circuit may also include a state machine. The state machine may transition the receiver from a high linearity mode to a low linearity mode if a set of operating conditions is satisfied. Similarly, the state machine may transition the transmitter from a high power mode to a low power mode if a set of operating conditions is satisfied.

Abstract: A wireless device configured for simultaneous voice and data communications is described. The wireless device includes a voice and data transceiver. The voice and data transceiver includes data path circuitry, voice path circuitry, a first multiplexer and a second multiplexer. The first multiplexer sends a primary data receive signal to the data path circuitry and receives a data transmit signal from the data path circuitry. The second multiplexer sends a diversity data receive signal to the data path circuitry, sends a voice receive signal to the voice path circuitry and receives a voice transmit signal from the voice path circuitry. The wireless device also includes a first antenna coupled to the first multiplexer. The wireless device further includes a second antenna coupled to the second multiplexer.

Abstract: Techniques for mitigating interference from a switching voltage regulator by intelligently varying the switcher frequency of the switching voltage regulator are provided. In one aspect, the switcher frequency is set by adjusting a frequency setting input to a programmable clock divider. In a further aspect, a processor drives a programmable clock divider which receives a value representative of a dividing factor by which to divide a reference clock frequency signal to generate a desired switcher frequency for the switching voltage regulator. Values of the programmable clock divider are selectively varied to achieve optimal performance and mitigate the effect of switcher frequency spurious content for a given operating condition or conditions.

Abstract: A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF VCO fine frequency tuning signal is monitored continuously to determine if the control voltage is within specified limits. If the RF VCO fine frequency tuning voltage is too low or too high for the RF VCO to meet system requirements or lock on the current desired frequency, an interrupt signal is asserted. In response to the interrupt signal, a wireless communications processor or a hardware state machine initiates coarse frequency calibration of the RF VCO at the desired frequency. After coarse frequency calibration has completed, the RF VCO fine frequency tuning voltage is within specified limits and is continuously monitored.

Abstract: A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF VCO fine frequency tuning signal is monitored continuously to determine if the control voltage is within specified limits. If the RF VCO fine frequency tuning voltage is too low or too high for the RF VCO to meet system requirements or lock on the current desired frequency, an interrupt signal is asserted. In response to the interrupt signal, a wireless communications processor or a hardware state machine initiates coarse frequency calibration of the RF VCO at the desired frequency. After coarse frequency calibration has completed, the RF VCO fine frequency tuning voltage is within specified limits and is continuously monitored.

Abstract: Techniques for mitigating interference from a switching voltage regulator by intelligently varying the switcher frequency of the switching voltage regulator are provided. In one aspect, the switcher frequency is set by adjusting a frequency setting input to a programmable clock divider. In a further aspect, a processor drives a programmable clock divider which receives a value representative of a dividing factor by which to divide a reference clock frequency signal to generate a desired switcher frequency for the switching voltage regulator. Values of the programmable clock divider are selectively varied to achieve optimal performance and mitigate the effect of switcher frequency spurious content for a given operating condition or conditions.

Abstract: An integrated circuit for achieving power reduction in a transceiver may include a jammer detector that determines an interference level corresponding to a received signal, and a transmit power detector that determines a required transmit power level for a transmitted signal. The integrated circuit may also include at least one of the following: a process monitor that determines process corners of components within the receiver and/or the transmitter, and a temperature monitor that determines a temperature of the receiver and/or the transmitter. The integrated circuit may also include a state machine. The state machine may transition the receiver from a high linearity mode to a low linearity mode if a set of operating conditions is satisfied. Similarly, the state machine may transition the transmitter from a high power mode to a low power mode if a set of operating conditions is satisfied.