Patents by Inventor Sai Chong Kwok

Sai Chong Kwok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7848713
    Abstract: Techniques for attenuating undesired signal components from a differential duplexer are described. The duplexer provides a differential received signal at RX+ and RX? ports. This differential received signal includes an undesired common mode signal, which may come from a transmit signal. The common mode signal is attenuated with a common mode trap in an impedance matching network coupled to the RX+ and RX? ports. The matching network includes a first passive circuit coupled between the RX+ port and a first node, a second passive circuit coupled between the RX? port and a second node, and the common mode trap coupled between the first and second nodes. In one design, the common mode trap includes a first inductor coupled between the first node and a common node, a second inductor coupled between the second node and the common node, and a capacitor coupled between the common node and circuit ground.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: December 7, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Jose Cabanillas, Prasad S. Gudem, Sai Chong Kwok, David Love
  • Publication number: 20090068963
    Abstract: Techniques for attenuating undesired signal components from a differential duplexer are described. The duplexer provides a differential received signal at RX+ and RX? ports. This differential received signal includes an undesired common mode signal, which may come from a transmit signal. The common mode signal is attenuated with a common mode trap in an impedance matching network coupled to the RX+ and RX? ports. The matching network includes a first passive circuit coupled between the RX+ port and a first node, a second passive circuit coupled between the RX? port and a second node, and the common mode trap coupled between the first and second nodes. In one design, the common mode trap includes a first inductor coupled between the first node and a common node, a second inductor coupled between the second node and the common node, and a capacitor coupled between the common node and circuit ground.
    Type: Application
    Filed: September 28, 2007
    Publication date: March 12, 2009
    Applicant: QUALCOMM INCORPORATED
    Inventors: Jose Cabanillas, Prasad S. Gudem, Sai Chong Kwok, David Love