Abstract: The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.

Abstract: The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.