Patents by Inventor Sai Hooi Yeong

Sai Hooi Yeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11910615
    Abstract: A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.
    Type: Grant
    Filed: May 23, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Han-Jong Chia, Feng-Cheng Yang, Bo-Feng Young, Nuo Xu, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11910617
    Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Han-Jong Chia, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin
  • Patent number: 11908936
    Abstract: A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Chieh Huang, Song-Fu Liao, Po-Ting Lin, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240055518
    Abstract: A transistor includes a gate electrode, a ferroelectric layer, a source pattern, a drain pattern, and a channel layer. The ferroelectric layer is disposed on the gate electrode. The source pattern and the drain pattern are disposed over the ferroelectric layer. The channel layer has a base and fins protruding from the base. The base is in contact with the ferroelectric layer. The fins are located between the source pattern and the drain pattern.
    Type: Application
    Filed: August 14, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Georgios Vellianitis, Sai-Hooi Yeong
  • Publication number: 20240055049
    Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, a plurality of static random access memory (SRAM) cells arranged in a second memory array, and a controller configured to access the first memory array and the second memory array with different access rate. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, a ferroelectric layer over the gate electrode, a first electrode over the gate electrode, and a second electrode over the first electrode. The ferroelectric layer is formed between the first and second electrodes.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Inventors: Han-Jong CHIA, Sai-Hooi YEONG, Yu-Ming LIN
  • Publication number: 20240055517
    Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chang Chiang, Yu-Chuan Shih, Chun-Chieh Lu, Po-Ting Lin, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240055349
    Abstract: A semiconductor memory structure includes a first cell including a first source structure and a first drain structure, a second cell including a second source structure and a second drain structure, a first bit line, a first source line, a second bit line and a second source line. The first source line is coupled to the first source structure. The first bit line is coupled to the first drain structure. The second source line is coupled to the second source structure. The second bit line is coupled to the second drain structure. The first source line and the first bit line are in a first common layer. The second bit line and the second source line are in a second common layer. A distance between the first source line and the first bit line is similar to a distance between the second source line and the second bit line.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Inventors: MENG-HAN LIN, SAI-HOOI YEONG, CHENCHEN WANG
  • Patent number: 11903221
    Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chenchen Wang, Chun-Chieh Lu, Chi On Chui, Yu-Ming Lin, Sai-Hooi Yeong
  • Patent number: 11901408
    Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
  • Patent number: 11901411
    Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11901450
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Bo-Feng Young, Chi On Chui, Chih-Yu Chang, Huang-Lin Chao
  • Patent number: 11903189
    Abstract: Three-dimensional memories are provided. A three-dimensional memory includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are divided into a plurality of groups, and the groups of memory cells are formed in respective levels stacked along a first direction. The word lines extend along a second direction, and the second direction is perpendicular to the first direction. Each of the bit lines includes a plurality of sub-bit lines formed in the respective levels. Each of the source lines includes a plurality of sub-source lines formed in respective levels. In each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chih-Yu Chang, Han-Jong Chia, Chenchen Jacob Wang, Yu-Ming Lin
  • Publication number: 20240021465
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first fin and a second fin on a semiconductor substrate. The semiconductor structure also includes an epitaxial structure on the first fin and the second fin. The semiconductor structure further includes outer spacers on outer sidewalls of the epitaxial structure. In addition, the semiconductor structure includes an inner spacer structure between the first fin and the second fin and covering inner sidewalls of the epitaxial structure. A top surface of the inner spacer structure is exposed to an air gap formed between the epitaxial structure and the inner spacer structure.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi YEONG, Yen-Chieh HUANG
  • Publication number: 20240023341
    Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 18, 2024
    Inventors: Mauricio Manfrini, Bo-Feng Young, Chun-Chieh Lu, Han-Jong Chia, Sai-Hooi Yeong
  • Publication number: 20240015976
    Abstract: In an embodiment, a device includes a first gate structure over a substrate, the first gate structure including a first gate electrode over a first side of a first gate dielectric; a first electrode and a second electrode disposed over a second side of the first gate dielectric opposite the first side; a second gate structure disposed between the first electrode and the second electrode, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric at least laterally surrounding the second gate electrode; and a semiconductor film disposed between the first electrode and the second electrode and at least laterally surrounding the second gate structure, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.
    Type: Application
    Filed: January 10, 2023
    Publication date: January 11, 2024
    Inventors: Meng-Han Lin, Sai-Hooi Yeong, Chia-En Huang, Chi On Chui
  • Publication number: 20240014214
    Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 11, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sai Hooi Yeong, Jody A. Fronheiser, Benjamin Colombeau, Balasubramanian Pranatharthiharan, El Mehdi Bazizi, Ashish Pal
  • Publication number: 20240015982
    Abstract: A device includes a memory layer over a substrate; a first source/drain structure and a second source/drain structure on the memory layer, wherein the first source/drain structure and the second source drain structure each include a first source/drain layer on the memory layer; a second source/drain layer on the first source/drain layer, wherein the second source/drain layer is different from the first source/drain layer; and a metal layer on the second source/drain layer; and a channel region extending on the memory layer from the first source/drain layer of the first source/drain structure to the first source/drain layer of the second source/drain structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: January 11, 2024
    Inventors: Meng-Han Lin, Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
  • Publication number: 20240015985
    Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Yu Chang, Han-Jong Chia
  • Patent number: 11869766
    Abstract: A method includes: providing a bottom layer; forming a first transistor over a substrate; forming a bottom electrode over the transistor; depositing a first seed layer over the bottom electrode; performing a surface treatment on the first seed layer, wherein after the surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11869971
    Abstract: A FeFET configured as a 2-bit storage device that includes a gate stack including a ferroelectric layer over a semiconductor substrate; and the ferroelectric layer includes dipoles; and a first set of dipoles at the first end of the ferroelectric layer has a first polarization; and a second set of dipoles at the second end of the ferroelectric layer has a second polarization, the first and second polarizations of the corresponding first and second sets of dipoles representing storage of 2 bits, wherein a first bit of the 2-bit storage device being configured to be read by application of a read voltage to the source region and a do-not-disturb voltage to the drain region; and a second bit of the 2-bit storage device being configured to be read by application of the do-not-disturb voltage to the source region and the read voltage to the drain region.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: January 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Chia-En Huang, Han-Jong Chia, Martin Liu, Sai-Hooi Yeong, Yih Wang