Abstract: A calibration wafer may bear one or more different mark types to facilitate inspection of a lithography process. A first mark type may be located on the outer peripheral portion of the wafer to indicate the desired boundary of an edge bead removal (EBR) region. A second mark type may be located on an outer peripheral portion of the wafer to indicate the desired boundary of a wafer edge expose region (WEE). A third mark type may indicate the border of a portion of the wafer expected to bear a wafer identification mark. A fourth mark type may be located at the center of the wafer to allow for precise and uniform application of liquid photoresist material to the calibration wafer. The calibration wafer may be employed in methods of rapidly and easily assessing the accuracy of various phases of photolithography processes.

Abstract: A calibration wafer may bear one or more different mark types to facilitate inspection of a lithography process. A first mark type may be located on the outer peripheral portion of the wafer to indicate the desired boundary of an edge bead removal (EBR) region. A second mark type may be located on an outer peripheral portion of the wafer to indicate the desired boundary of a wafer edge expose region (WEE). A third mark type may indicate the border of a portion of the wafer expected to bear a wafer identification mark. A fourth mark type may be located at the center of the wafer to allow for precise and uniform application of liquid photoresist material to the calibration wafer. The calibration wafer may be employed in methods of rapidly and easily assessing the accuracy of various phases of photolithography processes.

Abstract: A method and apparatus to eliminate contaminants in a lithography process for fabrication of integrated circuit devices. The method includes depositing a photoresist material on surface of a semiconductor substrate. A purge gas flow is provided proximate to an optical element to prevent a vapor from the exposed photoresist material from coming into contact with the optical element. In one embodiment, the purge gas flows into a perforated and open ended enclosure in which the optical element is provided in the form of a lens. One open end of the enclosure is coupled to the lens and the other open end is positioned above the surface of the semiconductor substrate. Perforation of the enclosure facilitates movement of purge gas thereto, eliminating contact with the vapor from the developed resist and unwanted deposition of a solid contamination on the lens.

Abstract: A method and apparatus to eliminate contaminants in a lithography process for fabrication of integrated circuit devices. The method includes depositing a photoresist material on surface of a semiconductor substrate. A purge gas flow is provided proximate to an optical element to prevent a vapor from the exposed photoresist material from coming into contact with the optical element. In one embodiment, the purge gas flows into a perforated and open ended enclosure in which the optical element is provided in the form of a lens. One open end of the enclosure is coupled to the lens and the other open end is positioned above the surface of the semiconductor substrate. Perforation of the enclosure facilitates movement of purge gas thereto, eliminating contact with the vapor from the developed resist and unwanted deposition of a solid contamination on the lens.