Abstract: Systems and methods for servicing read requests may include receiving a transaction from a processing unit while mirroring contents from an external memory to an on-chip RAM. Such systems and methods may monitor a progress of the mirroring and, based on the monitoring, access code or data values for the transaction from either the external memory or the on-chip RAM. Such systems and methods may further provide the code or data values to the processing unit according to the transaction. Such systems and methods may allow for execution of software before software has been fully downloaded to internal memory.

Abstract: Systems and methods for updating firmware may include using wait states to reduce or eliminate polling by an executing firmware component. An example includes dedicated firmware update hardware logic components, including a firmware update processing unit that executes firmware update code. The firmware update code may be paused between request of a hardware event and completion of a hardware event and under control of one or more of the hardware logic components. Once a hardware event has been completed, a hardware logic component may determine completion and, in response, restart execution of the firmware update code.

Abstract: An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.

Abstract: A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.

Abstract: A serial peripheral interface (SPI) module includes a transceiver including a clock line, a data line and at least one slave select line. The module also includes an interface circuit configured to monitor the slave select line and assert a fault based upon an incorrect de-assertion of the slave select line.

Abstract: A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.

Abstract: A synchronous serial peripheral device has a transmission unit coupled with a data output line and a clock unit coupled with a clock line. The serial peripheral device transmits a minimum of a single transmission, wherein in a first operating mode the transmission unit and the clock unit are configurable to perform a data transmission with a data length that can be defined to be between one (1) and eight (8) bit.