Abstract: Methods, systems, and devices for data protection techniques in stacked memory architectures are described. A memory system having a stacked memory architecture may include error correction information associated with a data set that includes multiple data segments stored across multiple memory arrays and, in some examples, multiple dies of the memory system. As part of a write operation for a first data segment of a data set, the memory system may retrieve the remaining data segments of the data set and calculate error correction information using the first data segment and the remaining data segments. As part of a read operation for a second data segment of the data set, the memory system may retrieve each data segment of the data set and perform an error correction operation on the data set using the error correction information.

Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

Abstract: Methods, systems, and devices for logical counters for a memory system are described. A controller within a memory system may generate one or more logical counters that each correspond to a management counter of a memory die. The controller may store the logical counters at a logical address space associated with the memory system. The logical address space may correspond to a physical location within a memory array of the memory die. The controller may periodically read a value of a management counter and store the value to the logical counter. In some examples, if the memory system detects an error condition for the management counter, the memory system may perform a recovery operation for the data stored at the memory die.

Abstract: Methods, systems, and devices for error tracking by a memory system are described. A memory system transmit indications of corrupt data without storing (e.g., internally storing) the indication. In some examples, a memory system may read data (e.g., from an associated memory device) and detect an error in the data. The memory system may generate an indication of the error and may transmit the indication to a host device. In other examples, a host device may transmit corrupted data with an indication of such. The memory system may store the corrupt data (e.g., an inverted version of the corrupt data) and, upon receiving a subsequent read command, may transmit the corrupt data to the host system with an indication that the data is corrupt.

Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.

Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.