Patents by Inventor Sai Krishna Mylavarapu
Sai Krishna Mylavarapu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11880275Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.Type: GrantFiled: August 17, 2022Date of Patent: January 23, 2024Assignee: Micron Technology, Inc.Inventor: Sai Krishna Mylavarapu
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Patent number: 11768633Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.Type: GrantFiled: October 13, 2022Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventor: Sai Krishna Mylavarapu
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Patent number: 11688467Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.Type: GrantFiled: June 14, 2021Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Zhengang Chen, Sai Krishna Mylavarapu, Zhenlei Shen, Tingjun Xie, Charles S. Kwong
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Publication number: 20230185660Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.Type: ApplicationFiled: February 13, 2023Publication date: June 15, 2023Inventors: Sai Krishna Mylavarapu, Todd A. Marquart
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Patent number: 11579964Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.Type: GrantFiled: December 22, 2020Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Sai Krishna Mylavarapu, Todd A. Marquart
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Publication number: 20230029959Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.Type: ApplicationFiled: October 13, 2022Publication date: February 2, 2023Inventor: Sai Krishna Mylavarapu
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Publication number: 20220391284Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.Type: ApplicationFiled: August 17, 2022Publication date: December 8, 2022Inventor: Sai Krishna Mylavarapu
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Patent number: 11494124Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.Type: GrantFiled: February 17, 2021Date of Patent: November 8, 2022Assignee: Micron Technology, Inc.Inventor: Sai Krishna Mylavarapu
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Patent number: 11429479Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.Type: GrantFiled: July 16, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventor: Sai Krishna Mylavarapu
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Publication number: 20220261184Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.Type: ApplicationFiled: February 17, 2021Publication date: August 18, 2022Inventor: Sai Krishna Mylavarapu
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Publication number: 20220197737Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Inventors: Sai Krishna Mylavarapu, Todd A. Marquart
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Publication number: 20220019502Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.Type: ApplicationFiled: July 16, 2020Publication date: January 20, 2022Inventor: Sai Krishna Mylavarapu
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Publication number: 20210304826Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.Type: ApplicationFiled: June 14, 2021Publication date: September 30, 2021Inventors: Zhengang Chen, Sai Krishna Mylavarapu, Zhenlei Shen, Tingjun Xie, Charles S. Kwong
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Patent number: 11048580Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.Type: GrantFiled: February 20, 2020Date of Patent: June 29, 2021Assignee: MICRON TECHNOLOGY, INC.Inventors: Samuel E. Bradshaw, Justin Eno, Sean Stephen Eilert, Sai Krishna Mylavarapu
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Patent number: 11037637Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).Type: GrantFiled: December 10, 2018Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Zhengang Chen, Sai Krishna Mylavarapu, Zhenlei Shen, Tingjun Xie, Charles S. Kwong
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Patent number: 10915256Abstract: A memory system may include a memory device and a controller. The memory device may include a plurality of storage areas. The controller may be suitable for processing data associated with at least one storage area among the plurality of storage areas of the memory device, and includes a logical to physical (L2P) table suitable for storing logical to physical (L2P) data, and a journal for storing update information indicating a change of logical to physical (L2P) information stored in the L2P table. The memory device may include a logical to physical (L2P) area corresponding to the L2P table of the controller such that, in the event of a power loss, the journal is written to the L2P area of the memory device and restored to the controller when power is restored.Type: GrantFiled: February 25, 2016Date of Patent: February 9, 2021Assignee: SK hynix Inc.Inventor: Sai Krishna Mylavarapu
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Publication number: 20200192750Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.Type: ApplicationFiled: February 20, 2020Publication date: June 18, 2020Inventors: Samuel E. Bradshaw, Justin Eno, Sean Stephen Eilert, Sai krishna Mylavarapu
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Publication number: 20200185045Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).Type: ApplicationFiled: December 10, 2018Publication date: June 11, 2020Inventors: Zhengang Chen, Sai Krishna Mylavarapu, Zhenlei Shen, Tingjun Xie, Charles S. Kwong
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Patent number: 10613925Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.Type: GrantFiled: May 18, 2018Date of Patent: April 7, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Samuel E. Bradshaw, Justin Eno, Sean Stephen Eilert, Sai krishna Mylavarapu
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Publication number: 20190354429Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.Type: ApplicationFiled: May 18, 2018Publication date: November 21, 2019Inventors: Samuel E. Bradshaw, Justin Eno, Sean Stephen Eilert, Sai Krishna Mylavarapu