Patents by Inventor Sai Ran Eom

Sai Ran Eom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9788438
    Abstract: The printed circuit board for the memory card includes an insulating layer; a mounting unit formed on a first surface of the insulating layer and electrically connected to a memory device; a terminal unit formed on a second surface of the insulating layer and electrically connected to electronic apparatuses of an outside; and metal layers formed at the mounting unit and the terminal unit and made of the same material.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 10, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Seol Hee Lim, Yun Kyoung Jo, Ae Rim Kim, Sai Ran Eom, Chang Hwa Park
  • Patent number: 9661750
    Abstract: Provided is a printed circuit board, including: a circuit pattern or a base pattern formed on an insulating layer; and a plurality of metal layers formed on the circuit pattern or the base pattern, wherein the metal layers includes: a silver metal layer formed of a metal material including silver; a first palladium metal layer formed at a lower part of the silver metal layer; and a second palladium metal layer formed at an upper part of the silver metal layer.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: May 23, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Yun Kyoung Jo, Seol Hee Lim, Chang Hwa Park, Sai Ran Eom, Ae Rim Kim
  • Patent number: 8956919
    Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 17, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hyun A. Chun, Jae Bong Choi, Sung Won Lee, Sung Wuk Ryu, Hyuk Soo Lee, Sai Ran Eom
  • Publication number: 20150000966
    Abstract: Provided is a printed circuit board, including: a circuit pattern or a base pattern formed on an insulating layer; and a plurality of metal layers formed on the circuit pattern or the base pattern, wherein the metal layers includes: a silver metal layer formed of a metal material including silver; a first palladium metal layer formed at a lower part of the silver metal layer; and a second palladium metal layer formed at an upper part of the silver metal layer.
    Type: Application
    Filed: November 30, 2012
    Publication date: January 1, 2015
    Inventors: Yun Kyoung JO, Seol Hee LIM, Chang Hwa PARK, Sai Ran EOM, Ae Rim KIM
  • Publication number: 20140369016
    Abstract: Provided is a printed circuit board for a memory card and a method of manufacturing the same, the printed circuit board for the memory card, including: an insulating layer; a mounting unit formed on a first surface of the insulating layer and electrically connected to a memory device; a terminal unit formed on a second surface of the insulating layer and electrically connected to electronic apparatuses of an outside; and metal layers formed at the mounting unit and the terminal unit and made of the same material.
    Type: Application
    Filed: December 12, 2012
    Publication date: December 18, 2014
    Inventors: Seol Hee Lim, Yun Kyoung Jo, Ae Rim Kim, Sai Ran Eom, Chang Hwa Park
  • Patent number: 8658471
    Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 25, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hyun A. Chun, Jae Bong Choi, Sung Won Lee, Sung Wuk Ryu, Hyuk Soo Lee, Sai Ran Eom
  • Publication number: 20120038036
    Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.
    Type: Application
    Filed: December 23, 2009
    Publication date: February 16, 2012
    Applicant: LG Innotek Co., Ltd.
    Inventors: Hyun A. Chun, Jae Bong Choi, Sung Won Lee, Sung Wuk Ryu, Hyuk Soo Lee, Sai Ran Eom