Abstract: An analog-to-digital converter (ADC) includes: a time-domain ADC core; and a calibration circuit. The time-domain ADC core includes: a first delay-to-digital stage having a terminal; a second delay-to-digital stage having a terminal; a third delay-to-digital stage having a terminal. The calibration circuitry is coupled to the terminal of the first delay-to-digital stage, the terminal of the second delay-to-digital stage, and the terminal of the third delay-to-digital stage of stages. The calibration circuitry is configured to calibrate the first delay-to-digital stage, the second delay-to-digital stage, and the third delay-to-digital stage based on a zero-crossing calibration and an over-range calibration. The over-range calibration sets a maximum threshold and a minimum threshold for the time-domain ADC relative to a reference voltage.