Patents by Inventor Sai-Weng Sin
Sai-Weng Sin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230012565Abstract: The present disclosure provides a control system of a buck converter, relating to the field of Internet of Things. The control system of a buck converter provided in an embodiment of the present disclosure includes a first control module, a second control module, and a mode selector. The first control module is turned on and the second control module is turned off through an analog current sensor in the mode selector when an IoT device switches from a transmission mode to a sleep mode or a standby mode, so that the first control module outputs a first voltage pulse to the driving and level shifter module, wherein a frequency of the first voltage pulse is determined by a frequency of a first clock in the first control module, and a width of the first voltage pulse is determined by a frequency of a second clock in the first control module.Type: ApplicationFiled: July 8, 2021Publication date: January 19, 2023Inventors: Wenliang ZENG, Chi Seng LAM, Sai Weng SIN, Weng Keong CHE, Rui Paulo Da Silva MARTINS, Ran DING
-
Patent number: 11545901Abstract: The present disclosure provides a control system of a buck converter, relating to the field of Internet of Things. The control system of a buck converter provided in an embodiment of the present disclosure includes a first control module, a second control module, and a mode selector. The first control module is turned on and the second control module is turned off through an analog current sensor in the mode selector when an IoT device switches from a transmission mode to a sleep mode or a standby mode, so that the first control module outputs a first voltage pulse to the driving and level shifter module, wherein a frequency of the first voltage pulse is determined by a frequency of a first clock in the first control module, and a width of the first voltage pulse is determined by a frequency of a second clock in the first control module.Type: GrantFiled: July 8, 2021Date of Patent: January 3, 2023Assignee: University of MacauInventors: Wenliang Zeng, Chi Seng Lam, Sai Weng Sin, Weng Keong Che, Rui Paulo Da Silva Martins, Ran Ding
-
Patent number: 10644718Abstract: An incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and the dynamic range (DR) is disclosed. The linear-exponential IADC includes an analog modulator and a decimation filter. The analog modulator has an input for receiving the analog input voltage and an output. The analog modulator includes an integrator, an adder, a quantizer, a noise-coupling path, a data weighted averaging (DWA) circuit, and a digital-to-analog converter (DAC). The decimation filter has an input for receiving signals from the output of the analog modulator. The decimation filter includes a 1st order accumulator, an exponential accumulator, and a decimator. The linear-exponential IADC is configured to operate with a linear phase for suppressing the thermal noise and an exponential phase for boosting the SQNR.Type: GrantFiled: May 7, 2019Date of Patent: May 5, 2020Assignee: University of MacauInventors: Biao Wang, Sai-Weng Sin, Franco Maloberti, Rui Paulo da Silva Martins
-
Patent number: 9692232Abstract: A mixed signal controller for a power quality compensator includes an analog circuit, an analog-to-digital converter (ADC), and a digital circuit. The analog circuit amplifies an input signal from the power quality compensator by a gain factor and outputs an analog signal, which is converted to a digital signal by the ADC. The digital circuit receives the digital signal, calculates the reference compensating current of each phase and then generates a trigger signal via hysteresis PWM to the power quality compensator. The digital circuit includes an evaluation circuit that calculates a value of the system total harmonic distortion after the power quality compensator compensates power and adjusts the gain factor when the value of the system total harmonic distortion reaches a predetermined threshold.Type: GrantFiled: July 24, 2016Date of Patent: June 27, 2017Assignee: University of MacauInventors: Man-Chung Wong, Chi-Seng Lam, Yan-Zheng Yang, Wai-Hei Choi, Ning-Yi Dai, Yajie Wu, Chi-Kong Wong, Sai-Weng Sin, U-Fat Chio, Seng-Pan U, Rui Paulo da Silva Martins
-
Publication number: 20170141571Abstract: A mixed signal controller for a power quality compensator includes an analog circuit, an analog-to-digital converter (ADC), and a digital circuit. The analog circuit amplifies an input signal from the power quality compensator by a gain factor and outputs an analog signal, which is converted to a digital signal by the ADC. The digital circuit receives the digital signal, calculates the reference compensating current of each phase and then generates a trigger signal via hysteresis PWM to the power quality compensator. The digital circuit includes an evaluation circuit that calculates a value of the system total harmonic distortion after the power quality compensator compensates power and adjusts the gain factor when the value of the system total harmonic distortion reaches a predetermined threshold.Type: ApplicationFiled: July 24, 2016Publication date: May 18, 2017Inventors: Man-Chung WONG, Chi-Seng LAM, Yan-Zheng YANG, Wai-Hei CHOI, Ning-Yi DAI, Yajie WU, Chi-Kong WONG, Sai-Weng SIN, U-Fat CHIO, Seng-Pan U, Rui Paulo da Silva MARTINS
-
Patent number: 8947283Abstract: A sampling front-end for analog to digital converter is presented that shares a high speed N-bit ADC at front-end and interleaves the pipelined residue amplification with shared amplifier, which achieves high speed, low power and compact area with high density capacitive DAC structure.Type: GrantFiled: June 12, 2013Date of Patent: February 3, 2015Assignee: University of MacauInventors: Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
-
Publication number: 20140368363Abstract: A sampling front-end for analog to digital converter is presented that shares a high speed N-bit ADC at front-end and interleaves the pipelined residue amplification with shared amplifier, which achieves high speed, low power and compact area with high density capacitive DAC structure.Type: ApplicationFiled: June 12, 2013Publication date: December 18, 2014Inventors: Yan ZHU, Chi-Hang CHAN, Sai-Weng SIN, Seng-Pan U, Rui Paulo da Silva MARTINS
-
Patent number: 8829942Abstract: A comparator is provided and the comparator includes a comparing input unit and a latching unit. Wherein, the comparing input unit has a first input receiving a first comparing signal and has a second input receiving a second comparing signal. The comparing input unit drives a first intermediate node signal at a first intermediate node depending on the first comparing signal according to a first strobe signal, and the comparing input unit drives a second intermediate node signal at a second intermediate node depending on the second comparing signal according to the first strobe signal. The latching unit determines a comparing result according to at least one of the first intermediate node signal and the second intermediate node signal. In addition, the latching unit latches the comparing result according to a second strobe signal.Type: GrantFiled: November 13, 2012Date of Patent: September 9, 2014Assignee: University of MacauInventors: Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
-
Publication number: 20140132307Abstract: A comparator is provided and the comparator includes a comparing input unit and a latching unit. Wherein, the comparing input unit has a first input receiving a first comparing signal and has a second input receiving a second comparing signal. The comparing input unit drives a first intermediate node signal at a first intermediate node depending on the first comparing signal according to a first strobe signal, and the comparing input unit drives a second intermediate node signal at a second intermediate node depending on the second comparing signal according to the first strobe signal. The latching unit determines a comparing result according to at least one of the first intermediate node signal and the second intermediate node signal. In addition, the latching unit latches the comparing result according to a second strobe signal.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: UNIVERSITY OF MACAUInventors: Chi-Hang CHAN, Yan ZHU, U-Fat CHIO, Sai-Weng SIN, Seng-Pan U, Rui Paulo da SILVA MARTINS
-
Patent number: 8659461Abstract: The present invention provides a pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) circuit with decoupled flip-around MDAC, capacitive attenuation solution and self-embedded offset cancellation. The flip-around MDAC architecture is built for low inter-stage gain implementation. A capacitive attenuation solution is provided for minimizing the power dissipation and optimizing conversion speed. The design reuses SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time.Type: GrantFiled: November 13, 2012Date of Patent: February 25, 2014Assignee: University of MacauInventors: Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
-
Patent number: 8466823Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.Type: GrantFiled: August 5, 2011Date of Patent: June 18, 2013Assignee: University of MacauInventors: U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
-
Patent number: 8441295Abstract: A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.Type: GrantFiled: November 4, 2011Date of Patent: May 14, 2013Assignee: University of MacauInventors: He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
-
Patent number: 8427355Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.Type: GrantFiled: September 14, 2011Date of Patent: April 23, 2013Assignee: University of MacauInventors: Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
-
Patent number: 8344931Abstract: The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.Type: GrantFiled: June 1, 2011Date of Patent: January 1, 2013Assignee: University of MacauInventors: Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Da Silva Martins, Franco Maloberti
-
Publication number: 20120306679Abstract: The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.Type: ApplicationFiled: June 1, 2011Publication date: December 6, 2012Applicant: University of MacauInventors: Yan ZHU, Chi-Hang CHAN, U-Fat CHIO, Sai-Weng SIN, Seng-Pan U, Rui Paulo Da Silva MARTINS, Franco MALOBERTI
-
Publication number: 20120286840Abstract: A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.Type: ApplicationFiled: November 4, 2011Publication date: November 15, 2012Applicant: University of MacauInventors: He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
-
Publication number: 20120229313Abstract: The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic.Type: ApplicationFiled: September 14, 2011Publication date: September 13, 2012Applicant: University of MacauInventors: Sai-Weng SIN, He-Gong WEI, Franco MALOBERTI, Li DING, Yan ZHU, Chi-Hang CHAN, U-Fat CHIO, Seng-Pan U, Rui Paulo da Silva MARTINS
-
Publication number: 20120194364Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.Type: ApplicationFiled: August 5, 2011Publication date: August 2, 2012Applicant: University of MacauInventors: U-Fat CHIO, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti