Patents by Inventor Sai Yu
Sai Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240172433Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chih-Yu CHANG, Han-Jong CHIA, Chenchen Jacob WANG, Yu-Ming LIN
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Patent number: 11991888Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.Type: GrantFiled: June 29, 2023Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Chih-Yu Chang, Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin
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Patent number: 11974441Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.Type: GrantFiled: December 30, 2020Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chih-Yu Chang, Chi On Chui, Yu-Ming Lin
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Publication number: 20240134980Abstract: A method for identifying malicious software includes receiving and executing a software application, identifying a plurality of uniform resource identifiers the software application interacts with during execution of the software application, and generating a vector representation for the software application using a feed-forward neural network configured to receive the plurality of uniform resource identifiers as feature inputs. The method also includes determining similarity scores for a pool of training applications, each similarity score associated with a corresponding training application and indicating a level of similarity between the vector representation for the software application and a respective vector representation for the corresponding training application.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Applicant: Google LLCInventors: Richard Cannings, Sai Deep Tetali, Mo Yu, Salvador Mandujano
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Patent number: 11955548Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.Type: GrantFiled: May 10, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mauricio Manfrini, Chih-Yu Chang, Sai-Hooi Yeong
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Publication number: 20240113202Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
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Publication number: 20240105847Abstract: A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.Type: ApplicationFiled: December 11, 2023Publication date: March 28, 2024Inventors: Pei-Yu WANG, Sai-Hooi YEONG
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Patent number: 11942523Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.Type: GrantFiled: February 13, 2023Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sai-Hooi Yeong, Pei-Yu Wang, Chi On Chui
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Publication number: 20240097010Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20240096928Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a MIM structure, a first contact and a second contact. The MIM structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, and a top electrode layer on the ferroelectric layer. The ferroelectric layer is substantially made of lead zirconate titanate (PZT), BaTiO3 (BTO), or barium strontium titanate (BST), and a thickness of the ferroelectric layer is greater than a thickness of the dielectric layer.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Inventors: SAI-HOOI YEONG, CHIH-YU CHANG, CHUN-YEN PENG, CHI ON CHUI
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Publication number: 20240096388Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chao-I WU, Chih-Yu CHANG, Yu-Ming LIN
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Publication number: 20240079472Abstract: The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Inventors: CHUN-YEN PENG, TE-YANG LAI, BO-FENG YOUNG, CHIH-YU CHANG, SAI-HOOI YEONG, CHI ON CHUI
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Patent number: 11919811Abstract: A curing agent for disposal of municipal solid waste incineration (MSWI) fly ash and a preparation method and use method thereof are provided. In the present disclosure, a loofah nanofiber crystal, a rice husk ash (RHA), sodium hydroxide, and water are adopted as raw materials to prepare the curing agent, and the curing agent can effectively realize the safe disposal and curing of heavy metals in an MSWI fly ash. The highest curing rates of the curing agent for heavy metals Pb2+, Zn2+, Cd2+, Cr3+, and Cu2+ can reach 99.7%, 99.4%, 99.5%, 98.7%, and 99.5%, respectively. The special three-dimensional (3D) cross-linked network structure of the loofah nanofiber crystal and the excellent physical and chemical adsorption properties and ion exchange capacity of the RHA are fully used in the curing agent of the present disclosure.Type: GrantFiled: April 25, 2023Date of Patent: March 5, 2024Assignee: DALIAN UNIVERSITY OF TECHNOLOGYInventors: Baomin Wang, Chengcheng Fan, Xiao Han, Tianru Li, Yunqing Xing, Xiong Zhang, Sai An, Ze Yu, Wanli Wang
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Patent number: 11916128Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.Type: GrantFiled: February 27, 2023Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 7215841Abstract: Provided are a method and a system, wherein optical beams of a plurality of wavelengths are directed through a plurality of optical devices, wherein waveguides comprising the optical devices have different fabrication errors, and wherein the waveguides have a plurality of waveguide lengths and a plurality of waveguide widths. Optical phase errors corresponding to the waveguides are measured by the optical devices. A determination is made of the components of the optical phase errors for the waveguides from the measured phase errors.Type: GrantFiled: December 21, 2004Date of Patent: May 8, 2007Assignee: Intel CorporationInventors: Everett X. Wang, Sai Yu, Yi Ding, Dmitri E. Nikonov
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Publication number: 20060133719Abstract: Provided are a method and a system, wherein optical beams of a plurality of wavelengths are directed through a plurality of optical devices, wherein waveguides comprising the optical devices have different fabrication errors, and wherein the waveguides have a plurality of waveguide lengths and a plurality of waveguide widths. Optical phase errors corresponding to the waveguides are measured by the optical devices. A determination is made of the components of the optical phase errors for the waveguides from the measured phase errors.Type: ApplicationFiled: December 21, 2004Publication date: June 22, 2006Inventors: Everett Wang, Sai Yu, Yi Ding, Dmitri Nikonov
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Patent number: 5859497Abstract: A stand-alone spacer for use in a flat-panel display includes a plurality of members being joined at a common axis. A first one of the members is a load-bearing member; a second one of the members is a stabilizing member. The load bearing member extends into the face plate and backplate of the display to provide standoff of mechanical forces. The load bearing member has an aspect ratio within the range of 2:1 to 20:1. The stand-alone spacer has a tipping angle within the range of 20 to 90 degrees so that, after placement on one of the display plates, the spacer is able to remain upright throughout the subsequent packaging and evacuation steps in the fabrication of the display.Type: GrantFiled: December 18, 1995Date of Patent: January 12, 1999Assignee: MotorolaInventors: Clifford L. Anderson, Lawrence N. Dworsky, Sai Yu