Abstract: The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA.

Abstract: The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the Class-S RF-PA. The drive circuit provides a high slew-rate, large-swing, quasi-digital gate drive circuit to drive the significant gate capacitance of the RF-PA with sufficient rise times. A combination of bipolar transistor current switches and cascoded CMOS devices is employed to attain requisite performance. For example, the driving circuit is well suited for use with Class-S RF-PAs used in wireless communication systems.

Abstract: A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.

Abstract: A electronic circuit with low inductance connections is disclosed. The electronic circuit includes a ground plane and a flex circuit. The flex circuit having a first surface generally facing the ground plane and a second surface opposite to the first surface. The flex circuit also having a flexible bridge defined thereof. The electronic circuit further includes a first electronic device communicatively coupled to the second surface of the flex circuit, a second electronic device communicatively coupled to the second surface of the flex circuit, and at least one conductive trace defined on the second surface of the flex circuit and extending along the flexible bridge. One end of the at least one conductive trace is configured for receiving an outbound current from the first electronic device and another end of the at least one conductive trace is communicatively coupled to the second electronic device through a vertical interconnect access.

Abstract: A method and system for synchronous transfer of bitstream data between a power-driver chip and a digital signal processing chip in a digital radio frequency transmit system is disclosed. A master phase-locked-loop located in the power-driver chip is utilized to provide master clocking control for the digital radio frequency transmit system. Furthermore, the clocking method and system is configurable to secure precise carrier frequency positioning of a digitally-generated radio frequency signal based on predetermined chip frequencies unrelated to the carrier frequency, assuring low bitstream phase noise at the output of the power driver chip.

Abstract: A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency.

Abstract: A system for providing a CMOS I/O circuit design that may replace existing bipolar I/O circuitry, and thus behave in substantially the same manner as bipolar I/O circuitry. Thus, an I/O circuit using a standard CMOS process is made that mimics operation of an ECL I/O circuit created using bipolar transistors. The CMOS input circuitry can receive input signals from an ECL output circuit, so as to mimic traditional ECL input circuitry. The CMOS output circuitry can output signals to an ECL input circuit, so as to mimic traditional ECL output circuitry. The CMOS I/O circuitry is designed to mimic the temperature dependent signals level, as present within traditional ECL I/O circuitry.

Abstract: A system for providing a CMOS I/O circuit design that may replace existing bipolar I/O circuitry, and thus behave in substantially the same manner as bipolar I/O circuitry. Thus, an I/O circuit using a standard CMOS process is made that mimics operation of an ECL I/O circuit created using bipolar transistors. The CMOS input circuitry can receive input signals from an ECL output circuit, so as to mimic traditional ECL input circuitry. The CMOS output circuitry can output signals to an ECL input circuit, so as to mimic traditional ECL output circuitry. The CMOS I/O circuitry is designed to mimic the temperature dependent signals level, as present within traditional ECL I/O circuitry.

Abstract: A method and system for generating a pair of synchronized clock signals is described. The system includes a first device connected between a first output voltage and an input reference voltage, wherein the first device generates a first output clock signal. Further, the system includes a second device connected in series with the first device. In particular, the second device is connected between the input reference voltage and a second output voltage, wherein the second device generates a second output clock signal. In addition, a first switching circuit is connected in parallel with the first device and a second switching circuit is connected in parallel with the second device. The first switching circuit operates to toggle the first device on and off and the second switching circuit operates to toggle the second device on and off. The first and second switching circuits are coupled to a comparator, which receives a first input clock and a second input clock signal.

Abstract: Variable gain amplifier (VGA) circuits and methods implemented in such circuits are disclosed. An example VGA circuit includes a differential transistor pair for receiving a differential input signal. The differential transistor pair, in operation, conducts a substantially constant current over a linear operating range of the variable gain amplifier circuit. The VGA circuit also includes a current source that is coupled with the differential transistor pair. The current source, in operation, provides the substantially constant current to the differential transistor pair. The VGA circuit further includes a variable resistance circuit coupled with the differential transistor pair. In operation, a resistance of the variable resistance circuit is adjusted such that a gain of the variable gain amplifier circuit is adjusted. Further, in operation, the VGA circuit produces a differential output signal, the differential output signal being an amplified version of the differential input signal.

Abstract: Mixer circuits with direct-current bias are disclosed. An example embodiment of such a mixer includes a first differential transistor pair and a second differential transistor pair. The example mixer also includes first and second local oscillator signal terminals and first and second mixed signal terminals. The first and second local oscillator signal terminals are coupled with the first and second differential transistor pairs. The first mixed signal terminal is coupled with the first differential pair and the second mixed signal terminal is coupled with the second differential pair. The mixer further includes first and second baseband signal terminals, where each baseband signal terminal is coupled with the first differential pair and the second differential pair. The mixer still further includes a first current source and a second current source.

Abstract: Signal coincidence detection circuits and methods implemented in such circuits are disclosed. An example signal coincidence detection circuit includes a first differential transistor pair, a second differential transistor pair coupled with the first differential transistor pair and a third differential transistor pair coupled with the first differential transistor pair in parallel with the second differential transistor pair. The circuit also includes a first input signal terminal coupled with the first, second and third differential transistor pairs, wherein, in operation, the first input signal terminal receives a first input signal that is communicated to the first, second and third differential transistor pairs.

Abstract: A mixer circuit is disclosed that includes a first mixer stage including first and second transmission gates. The mixer circuit also includes a second mixer stage including third and fourth transmission gates. The mixer further includes a first base band signal terminal coupled with the first and second transmission gates and a second base band signal terminal coupled with the third and fourth transmission gates. The mixer circuit processes signals so as to mix a base band signal communicated to the first and second base band signal terminals with a differential LO signal communicated to first and second LO signal terminals to create a first mixed differential signal. Alternatively, the mixer extracts a base band signal from a mixed signal communicated to the first and second mixed signal terminals signal using the LO signal communicated to the first and second LO signal terminals.

Abstract: A mixer circuit in accordance with an embodiment of the invention includes a first mixer stage including first and second transmission gates, and a second mixer stage including third and fourth transmission gates. The mixer further includes a first base band signal terminal coupled with the first and second transmission gates and a second base band signal terminal coupled with the third and fourth transmission gates. The mixer circuit processes signals so as to mix a base band signal communicated to the first and second base band signal terminals with a differential LO signal communicated to first and second LO signal terminals to create a first mixed differential signal. Alternatively, the mixer extracts a base band signal from a mixed signal communicated to the first and second mixed signal terminals signal using the LO signal communicated to the first and second LO signal terminals.