Abstract: A non-volatile memory device is fabricated having enhanced charge retention capability. Enhanced charge retention is achieved upon the floating gate of the non-volatile memory device. The floating gate can be configured as a stacked or non-stacked pair of polysilicon conductors. In either instance, negative charge programmed upon the floating gate is retained by reducing the presence of positively charged atoms within dielectrics overlying the floating gate conductor. Moreover, diffusion avenues of the positively charged hydrogen are reduced by maintaining a prevalence of relatively strong bond locations within the overlying dielectric layers. Thus, origination of positively charged atoms such as hydrogen from those bonds is substantially prevented by processing the hydrogen-containing dielectrics at relatively low temperatures and further processing any subsequent dielectrics and/or conductors overlying the floating gate at relatively low temperatures.

Abstract: A non-volatile memory device is fabricated having enhanced charge retention capability. Enhanced charge retention is achieved upon the floating gate of the non-volatile memory device. The floating gate maybe can configured as a stacked or non-stacked pair of polysilicon conductors. In either instance, negative charge programmed upon the floating gate is retained by reducing the presence of positively charged atoms within dielectrics overlying the floating gate conductor. Moreover, diffusion avenues of the positively charged hydrogen are reduced by maintaining a prevalence of relatively strong bond locations within the overlying dielectric layers. Thus, origination of positively charged atoms, such as hydrogen, from those bonds are substantially prevented by processing the hydrogen-containing dielectrics at relatively low temperatures and further processing any subsequent dielectrics and/or conductors overlying the floating gate at relatively low temperatures.

Abstract: An improved method of silicon wafer fabrication suitable for either CMOS and/or NMOS process flows. The present method utilizes few processing steps to reduce fabrication costs and enhance wafer throughput. The improved method combines sacrificial oxide growth and removal steps of CMOS and NMOS front end pre-oxide steps with existing pad oxide growth and removal steps, resulting in fewer required operations. The thermal cycles required to form gettering sites within Cz bulk silicon wafers are retained, thus allowing the number of required processing operations to be reduced without negatively impacting existing levels of expected production yields.