Abstract: A method and system is disclosed for controlling cooling unit operational settings according to a desired useful life target. The method and system includes an adaptive cooling controller which uses system configuration information to associate a particular cooling unit with particular sub-equipment locations, and further uses configuration information to associate cooling unit activity with respective sensors. At a given cooling unit setting, the adaptive cooling controller determines from sensor readings in the associated sub-equipment whether a cooling unit setting change is required according to the configuration information for the sub-equipment in conjunction with a useful life target. The method and system is particularly useful for overcoming the difficulty with accommodating sub-equipment changes of cooling unit controllers known in the art.

Abstract: A method and system is disclosed for controlling cooling unit operational settings according to a desired useful life target. The method and system includes an adaptive cooling controller which uses system configuration information to associate a particular cooling unit with particular sub-equipment locations, and further uses configuration information to associate cooling unit activity with respective sensors. At a given cooling unit setting, the adaptive cooling controller determines from sensor readings in the associated sub-equipment whether a cooling unit setting change is required according to the configuration information for the sub-equipment in conjunction with a useful life target. The method and system is particularly useful for overcoming the difficulty with accommodating sub-equipment changes of cooling unit controllers known in the art.

Abstract: A method and system is disclosed for controlling cooling unit operational settings according to power dissipation levels in sub-equipment. The method and system includes an adaptive cooling controller which uses system configuration information to associate a particular cooling unit with particular sub-equipment, and further uses configuration information to associate cooling unit activity with respective sensors. At a given cooling unit setting, the adaptive cooling controller determines from sensor readings in the associated sub-equipment whether a cooling unit setting change is required according to the configuration information for the sub-equipment. The sensor readings may include both temperature and power dissipation readings. The method and system is particularly useful for overcoming the difficulty with accommodating sub-equipment changes of cooling unit controllers known in the art.

Abstract: A method and system is disclosed for controlling cooling unit operational settings according to a desired useful life target. The method and system includes an adaptive cooling controller which uses system configuration information to associate a particular cooling unit with particular sub-equipment locations, and further uses configuration information to associate cooling unit activity with respective sensors. At a given cooling unit setting, the adaptive cooling controller determines from sensor readings in the associated sub-equipment whether a cooling unit setting change is required according to the configuration information for the sub-equipment in conjunction with a useful life target. The method and system is particularly useful for overcoming the difficulty with accommodating sub-equipment changes of cooling unit controllers known in the art.

Abstract: Apparatus and methods for autonomously identifying and mitigating soft-errors affecting integrated circuit memory storage devices are provided. A soft-error mitigation process is invoked upon finding that an integrated circuit memory device is affected by a parity error. In a staged approach, unused memory regions of the integrated circuit memory device are reinitialized; if a redundant deployment prevails, the subsystem corresponding to the affected integrated circuit memory device is reset; memory regions having copies of contents thereof stored at remote locations are rewritten with obtained copies of the contents; and memory regions storing contents which are generated at run-time are reinitialized. Directed parity error scans are employed at each stage. If the parity error persists, one of the apparatus, and the subsystem corresponding to the affected silicon memory device is reset during a maintenance window.

Abstract: Interconnected networking systems is becoming a challenge in terms of dependability estimation as two main communication technologies co-exist in today's networks: switching and routing. These two technologies have two different and complementary levels of resilience. Switching is focused on sensitivity to delays and connectivity whereas routing is focused on traffic losses and traffic integrity. The main challenge in modeling these systems dependability is to aggregate the complexity and interactions from various layers of network functions and work with a viable model that reflects the resilience behavior from the service provider and the service user standpoints. The method uses a hierarchical approach based on the Markov Chains and RBD modeling techniques to build a multi-layered model of assuring a multi-services networking system meets its reliability targets dictated by a service level agreement.

Abstract: Apparatus and methods for autonomously identifying and mitigating soft-errors affecting integrated circuit memory storage devices are provided. A soft-error mitigation process is invoked upon finding that an integrated circuit memory device is affected by a parity error. In a staged approach, unused memory regions of the integrated circuit memory device are reinitialized; if a redundant deployment prevails, the subsystem corresponding to the affected integrated circuit memory device is reset; memory regions having copies of contents thereof stored at remote locations are rewritten with obtained copies of the contents; and memory regions storing contents which are generated at run-time are reinitialized. Directed parity error scans are employed at each stage. If the parity error persists, one of the apparatus, and the subsystem corresponding to the affected silicon memory device is reset during a maintenance window.