Abstract: An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied.

Abstract: An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied.

Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

Abstract: A magnetic layer (46) of a magnetoelectronics element (40) is provided that has a first sub-element layer (48) and a second sub-element layer (50). The first sub-element layer (48) is configured to have a first area and the second sub-element layer (50) is configured to have a second area that is less than the first area.

Abstract: An MTJ cell including an insulator layer of material between magnetic material layers with the insulator layer of material having a greater attraction for a third material than the magnetic material layers. The third material is introduced to one or both so that when the cell is heated the third material is redistributed from the magnetic material layer to the insulator layer. Upon redistribution the insulator layer becomes an insulator layer material. Also, a first diffusion barrier layer is positioned between a first metal electrode and one of the magnetic material layers and/or a second diffusion barrier layer is positioned between a second metal electrode and the other magnetic material layer to prevent diffusion of the metal in the electrodes into the magnetic material layers.

Abstract: A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.

Abstract: A magnetic memory cell (10) has a semiconductor layer (12) positioned between first (11) and second (13) ferromagnetic layers forming either a p-n or Schottky junction. A magnetic layer (34) is positioned between the first ferromagnetic layer and a digit line (first) for pinning a magnetic vector within the second ferromagnetic layer. In a 13 embodiment, a gate contact (37) is spaced apart from the layer of semiconductor material for controlling the electron flow through the semiconductor layer.

Abstract: An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) includes a fixed ferromagnetic layer (26). A second electrode (18) is included and comprises a free ferromagnetic layer (28). A spacer layer (16) is located between the fixed ferromagnetic layer (26) and the free ferromagnetic (28) layer, the spacer layer (16). At least one additional layer (20 & 22) is provided between the base metal layer (13) and the spacer layer (16). The base metal layer (13) or at least one of the layers positioned between the base metal layer (13) and the spacer layer (16) having an x-ray amorphous structure such that a reduced topological coupling strength between the free ferromagnetic layer (28) and the fixed ferromagnetic layer (26) is achieved.

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by barrier layers comprising wide bandgap material (18) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a N-type drain region (22b). Each channel is also coupled to an N-type source region (25b). With appropriate gate bias on a gate electrode (17), quantized energy levels in the channels (12, 14, 16) are aligned to provide self-doping by electrons in the valence band of the P-channel (14) moving to the conduction band of the N-channels (12, 16) providing peak channel conductivity. At higher gate bias, one of the N-channels (12) becomes non-conductive creating a negative resistance region.

Abstract: A complementary field effect structure having a first field effect device (26) including a quantum well having a first channel (12). A first doping region (14) is positioned adjacent to a first quantum well and a first gate electrode (29) is positioned so that the first doping region (14) is between the first gate electrode (29) and the first channel (12) . A second field effect device (37) includes a second channel (22) and a second doping region (19) positioned adjacent to the second channel. A second gate electrode (31) is positioned over the second channel (22) so that the second channel (22) is between the second gate electrode (31) and the second doping region (19). An interconnect electrically couples the first gate electrode (29) to the second gate electrode (31).

Abstract: A semiconductor structure that provides intrinsic doping from native defects is provided. A quantum well including a narrow bandgap material (11, 14) having a low concentration of native defects is sandwiched between two wide bandgap spacer layers (12, 20, 17, 15). The spacer layers (12, 20, 17, 15) have a low concentration of native defects. At least one doping region (13, 16) having a high concentration of native defects positioned adjacent to one of the undoped spacer layers (12, 17).

Abstract: A semiconductor device having a vertical interconnect or via stacked formed by quantum well comprising a semiconductor material is provided. A first semiconductor device (11) having a current carrying region (19) is formed in a first horizontal plane. A second semiconductor device (12) having a current carrying region (29) is formed in a second horizontal plane. Each of the current carrying regions have a first quantized energy level that is substantially equal. A semiconductor via (31) couples the current carrying region (19) of the first semiconductor device (11) to the current carrying region (29) of the second device (12), wherein the semiconductor via (31) has a first quantized energy level capable of alignment with the quantized energy levels of the current carrying regions (19, 29) of the first and second semiconductor devices (11,12).

Abstract: A semiconductor device having a lateral interconnect or via formed by quantum well comprising a semiconductor material is provided. The lateral interconnect (17, 18, 19) formed by a quantum well comprising a first semiconductor material composition. A first semiconductor region (11, 12, 13) comprising a second material type is formed adjacent to the lateral interconnect (17, 18, 19). A second semiconductor region (23, 24, 26) comprising the second material type is adjacent to the lateral interconnect (17, 18, 19) so that the lateral interconnect (17, 18, 19) separates the first (11, 12, 13) and second (23, 24, 26) semiconductor regions. The first (17, 18, 19) and second (23, 24, 26) semiconductor regions have a first quantized energy level that is substantially equal. The lateral interconnect (17, 18, 19) has a first quantized energy level capable of alignment with the quantized energy levels of the first (11, 12, 13) and second (23, 24, 26) semiconductor regions.

Abstract: A resonant tunneling semiconductor device having two large bandgap barrier layers (12, 14) separated by a quantum well (13) is provided. The two barriers (12,14) and the quantum well (13) are formed between first and second semiconductor layers (11, 16) of a first conductivity type. A monolayer (17) of material having a different bandgap than the quantum well material is provided in the quantum well thereby lowering the ground state energy level of the quantum well. Alternatively, monolayers (18, 19) having a different bandgap than that of the first and second semiconductor layers (11, 16) are formed in the first and second semiconductor layers, respectively, outside of the quantum well (13).

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by independent gate electrodes (13, 15) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a drain electrode (21). Each channel is also coupled to a source electrode (25-26). The quantum well channels (12, 14, 16) and quantum well gates (13, 15) are separated from each other by barrier layers (18) of a wide bandgap semiconductor material.