Abstract: A display system of a display includes multiple primary light emitting diodes and multiple secondary light emitting diodes. The multiple primary light emitting diodes may emit light, in which at least a first primary light emitting diode of the multiple primary light emitting diodes is shorted. Moreover, the multiple secondary light emitting diodes may emit light. At least a first secondary light emitting diode of the multiple secondary light emitting diodes is associated with the first primary light emitting diode, and the first secondary light emitting diode may emit light based at least in part on the first primary light emitting diode being shorted.

Abstract: To reduce image artifacts and non-uniformity associated with a display pixel of an electronic display, processing circuity may adjust a luminance value corresponding to a display pixel according to a per-pixel gain mask, a per-pixel anode mask, or both. To further correct for the non-uniformity, the processing circuitry may convert the luminance value to a digital code based on a curve associated with an anode on which the display pixel is located.

Abstract: A pulse width modulation and amplitude modulation driving system for a display panel, including related circuits and methods of operation, are described. In an embodiment, a display panel includes a thin film transistor layer comprising a plurality of subpixel circuits. Each subpixel circuit may include a drive transistor, a comparator, and a switch. A plurality of light emitting diodes (LEDs), such as micro-LEDs, may be connected to the plurality of subpixel circuits. Each subpixel circuit can control an LED based on a current amplitude controlled by the drive transistor and a current pulse width controlled by the comparator and the switch. Other aspects are also described and claimed.

Abstract: To reduce image artifacts and non-uniformity associated with a display pixel of an electronic display, processing circuity may adjust a luminance value corresponding to a display pixel according to a per-pixel gain mask, a per-pixel anode mask, or both. To further correct for the non-uniformity, the processing circuitry may convert the luminance value to a digital code based on a curve associated with an anode on which the display pixel is located.

Abstract: Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

Abstract: A display system of a display includes a first light emitting diode, a second light emitting diode, a current source, and at least one transistor. The first and the second light emitting diodes emit light. The current source provides a constant current to the first light emitting diode and the second light emitting diode. Moreover, the at least one transistor removes the current or shunts the current towards the first light emitting diode, the second light emitting diode, or both. Removing the current or shunting the current towards the first light emitting diode, the second light emitting diode, or both, may blend outputs of the first light emitting diode and the second light emitting diode.

Abstract: A display device includes a voltage source that provides a voltage and a current source that provides a current. The display device also includes light emitting diodes (LEDs) that emit light to display an image on the display device. Additionally, the display device includes pixel driving circuitry that drives the LEDs using the voltage or the current. In particular, the pixel driving circuitry provides the LEDs with the voltage from the voltage source for a first period of time to enable the LEDs to reach an illumination threshold. Moreover, the pixel driving circuitry, after providing the voltage from the voltage source for the first period of time, drives the LEDs using the current from the current source to cause the LEDs to emit light substantially uninterrupted when changing between providing the voltage from the voltage source to driving the one or more LEDs using the current source.

Abstract: A display system of a display includes multiple primary light emitting diodes and multiple secondary light emitting diodes. The multiple primary light emitting diodes may emit light, in which at least a first primary light emitting diode of the multiple primary light emitting diodes is shorted. Moreover, the multiple secondary light emitting diodes may emit light. At least a first secondary light emitting diode of the multiple secondary light emitting diodes is associated with the first primary light emitting diode, and the first secondary light emitting diode may emit light based at least in part on the first primary light emitting diode being shorted.

Abstract: Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

Abstract: Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

Abstract: Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

Abstract: Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

Abstract: Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

Abstract: Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

Abstract: A method and system for staggered parallelized video decoding system decodes a compressed video stream at approximately double the performance of conventional systems, and outputs the decoded stream to a video display device. Even and odd video frames from the video stream are identified and stored in a memory. A first decoder processes a first portion of a first even frame from among the stored even frames. After the first decoder completes processing the first portion of the first even frame, a second decoder begins processing a first odd frame from among the stored odd frames. The processing start times of the odd frames are staggered with respect to the even frames and vice versa, and the even and odd frames are simultaneously processed using first and second decoders.

Abstract: A method and system for staggered parallelized video decoding system decodes a compressed video stream at approximately double the performance of conventional systems, and outputs the decoded stream to a video display device. Even and odd video frames from the video stream are identified and stored in a memory. A first decoder processes a first portion of a first even frame from among the stored even frames. After the first decoder completes processing the first portion of the first even frame, a second decoder begins processing a first odd frame from among the stored odd frames. The processing start times of the odd frames are staggered with respect to the even frames and vice versa, and the even and odd frames are simultaneously processed using first and second decoders.

Abstract: A method and system for staggered parallelized video decoding system decodes a compressed video stream at approximately double the performance of conventional systems, and outputs the decoded stream to a video display device. Even and odd video frames from the video stream are identified and stored in a memory. A first decoder processes a first portion of a first even frame from among the stored even frames. After the first decoder completes processing the first portion of the first even frame, a second decoder begins processing a first odd frame from among the stored odd frames. The processing start times of the odd frames are staggered with respect to the even frames and vice versa, and the even and odd frames are simultaneously processed using first and second decoders.

Abstract: A system and method for determining a preferred motion vector is provided, which may be used to estimate motion in a series of video image frames. The system may include a video encoder having a motion vector selector. The motion vector selector may include a first generator to generate a cost associated with motion vectors in a first direction, a selector to set a cross over point corresponding to a lowest cost motion vector in the first direction, a direction indicator to sample a set of motion vectors about the cross over point to select a preferred direction, and a second generator to generate a cost associated with the motion vectors in the preferred direction. The method may include determining a final motion vector having the lowest cost within a search window.

Abstract: A non-buffered video line memory eliminates the need for double buffering video data during processing. While most double buffering systems double the amount of memory necessary to store video data, a non-buffered approach reduces the hardware memory costs substantially. A set of write and read pointers coupled with write and read incrementors allows data to be stored in raster order and removed in block order from a non-buffered memory device. The incrementors, in conjunction with a set of write and read pointers generate a base address for data to be written to and read from the non-buffered memory at substantially the same time. Encoding systems benefit substantially by being able to read and write information into a common memory rather than continuously switching between two different memories, by reducing complexity and cost.

Abstract: A system and method for determining a preferred motion vector is provided, which may be used to estimate motion in a series of video image frames. The system may include a video encoder having a motion vector selector. The motion vector selector may include a first generator to generate a cost associated with motion vectors in a first direction, a selector to set a cross over point corresponding to a lowest cost motion vector in the first direction, a direction indicator to sample a set of motion vectors about the cross over point to select a preferred direction, and a second generator to generate a cost associated with the motion vectors in the preferred direction. The method may include determining a final motion vector having the lowest cost within a search window.