Abstract: The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an address pipeline to transfer multiple data words by the spill control unit and the fill control unit to improve the throughput of spill and fill operations. When new data words are written to the top memory location of the stack, the optop pointer is incremented. If data words are read off the stack the optop pointer is decremented. During normal operations the dribble manager unit detects spill conditions and fill conditions.

Abstract: An instruction pipeline is provided which can handle stack cache misses without stalling. The instruction pipeline includes a stack cache fetch stage configured to retrieve data from a stack cache and a data cache fetch stage configured to retrieve data from a data cache. The instruction pipeline writes data out during a write stage that occurs at the end of the instruction pipeline. Thus, instead of stalling on a stack cache miss, the instruction pipeline can continue processing and issuing a data cache request in the data cache fetch stage for the required data. In addition, some embodiments of the invention include a feedback path between the stack cache fetch stage and pipeline stages following the stack cache fetch stage. If the stack cache fetch stage requires data from an address that is also being used by a later pipeline stage, the data in the later pipeline stage is sent to the stack cache fetch stage through the feedback path.

Abstract: An execution unit for a stack based computing system that can combine instructions into instruction groups for concurrent execution is provided. In accordance with one embodiment, the instructions of the stack based computing system are separated into different instruction types. Certain combinations of instruction types can be combined into instruction groups for concurrent execution. The execution unit includes an instruction folding unit that is configured to determine the instruction type of instructions and combine the instructions into instruction groups, and an instruction pipeline that is configured to process both instructions and instruction groups. In one embodiment, the instruction folding unit includes: an instruction type estimator which estimates the instruction types of various instructions; an instruction selector, which selects the instruction types from the estimated instruction types; and a folding logic circuit which combines the instructions into instruction groups.

Abstract: A length decoder that rapidly calculates the group lengths of groups of variable length data words is provided. In accordance with one embodiment, a length decoder includes a length estimator and a length selector. The length estimator, estimates a length for each data word assuming the data word is the first member of a group. The length selector then selects the proper estimate based upon the actual length of the data word. Specifically, one embodiment of the length decoder can be used to calculate the length of instruction groups in a stack based computing system.

Abstract: The present invention provides a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit suspends operation of the stack cache and causes the spill control unit to store the valid data words in the slow memory unit or data cache unit. After the valid data in the stack cache are saved, the overflow/underflow unit equates the cache bottom pointer to the optop pointer.

Abstract: The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit resolves the overflow by suspending operation of the stack cache and spilling a plurality of data words from the stack cache to the stack and equating the bottom pointer to the optop pointer. Typically, the overflow/underflow unit spills all valid data words from the stack cache during an overflow.

Abstract: An execution unit that executes multiple instructions as a single instruction group during a single processing cycle is provided. The execution unit handles problem causing instruction groups by trapping the problem causing instruction group using the trap logic of a processing unit. The reissue logic circuits restores the program state of the execution unit prior to issuance of the trapped instruction group. The reissue logic circuit then forces each instruction of the instruction group to be issued as a separate instruction. Specifically, the reissue logic inhibits folding of instructions into instruction groups by an instruction-folding unit. After the instructions of the trapped instruction group are executed, the reissue logic re-enables folding by the instruction-folding unit.

Abstract: A stack management unit includes a stack cache to accelerate data retrieval from a stack and data storage into the stack. The stack management unit also includes an address pipeline to transfer multiple data words by a spill control unit and a fill control unit in the stack management unit. The address pipeline contains an incrementor/decrementor circuit, a first address register and a second address register. An address multiplexer drives either the output signal of the incrementor/decrementor or a cache bottom pointer to the first address register. The output terminals of the first address register are coupled to the input terminals of the second address register. A stack cache multiplexer drives either the address in the first address register or the address in the second address register to the stack cache. A memory multiplexer drives either the address in the address multiplexer or in the first address register to a slow memory unit.