Patents by Inventor Sailesh Kottapalli
Sailesh Kottapalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11048588Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.Type: GrantFiled: February 11, 2020Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
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Publication number: 20200257609Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.Type: ApplicationFiled: February 11, 2020Publication date: August 13, 2020Applicant: Intel CorporationInventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
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Patent number: 10599547Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.Type: GrantFiled: November 30, 2017Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
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Patent number: 10387151Abstract: Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.Type: GrantFiled: September 30, 2011Date of Patent: August 20, 2019Assignee: Intel CorporationInventors: Jonathan C. Hall, Sailesh Kottapalli, Andrew T. Forsyth
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Patent number: 10204049Abstract: Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.Type: GrantFiled: January 6, 2012Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Vedaraman Geetha, Jeffrey D. Chamberlain, Sailesh Kottapalli, Ganesh Kumar, Henk G. Neefs, Neil J. Achtman, Bongjin Jung
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Publication number: 20180157575Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.Type: ApplicationFiled: November 30, 2017Publication date: June 7, 2018Inventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
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Publication number: 20180081808Abstract: Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.Type: ApplicationFiled: January 6, 2012Publication date: March 22, 2018Applicant: INTEL CORPORATIONInventors: Vedaraman GEETHA, Jeffrey D. CHAMBERLAIN, Sailesh KOTTAPALLI, Ganesh KUMAR, Henk G. NEEFS, Neil J. ACHTMAN, Bongjin JUNG
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Patent number: 9858167Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.Type: GrantFiled: December 17, 2015Date of Patent: January 2, 2018Assignee: Intel CorporationInventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
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Publication number: 20170177460Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.Type: ApplicationFiled: December 17, 2015Publication date: June 22, 2017Inventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
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Patent number: 9436605Abstract: An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M?) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.Type: GrantFiled: December 20, 2013Date of Patent: September 6, 2016Assignee: INTEL CORPORATIONInventors: Jeffrey D. Chamberlain, Vedaraman Geetha, Robert G. Blankenship, Yen-Cheng Liu, Adrian C. Moga, Herbert H. Hum, Sailesh Kottapalli
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Patent number: 9423959Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.Type: GrantFiled: June 29, 2013Date of Patent: August 23, 2016Assignee: Intel CorporationInventors: Subramanya R. Dulloor, Sanjay Kumar, Rajesh M. Sankaran, Gilbert Neiger, Richard A. Uhlig, Robert S. Chappell, Joseph Nuzman, Kai Cheng, Sailesh Kottapalli, Yen-Cheng Liu, Mohan Kumar, Raj K. Ramanujan, Glenn J. Hinton
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Patent number: 9405595Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.Type: GrantFiled: July 24, 2014Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Sailesh Kottapalli, John H. Crawford
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Patent number: 9298629Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.Type: GrantFiled: November 21, 2014Date of Patent: March 29, 2016Assignee: Intel CorporationInventors: Sailesh Kottapalli, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Dheemanth Nagaraj
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Patent number: 9201748Abstract: Systems and techniques for virtual device sharing. A failure of one of a plurality of memory devices corresponding to a first rank in a memory system is detected. The memory system has a plurality of ranks, each rank having a plurality of memory devices used to store a cache line. A portion of the cache line corresponding to the failed memory device is stored in a memory device in a second rank in the memory system and the remaining portion of the cache line in the first rank of the memory system.Type: GrantFiled: March 30, 2012Date of Patent: December 1, 2015Assignee: Intel CorporationInventors: Brian S. Morris, Sailesh Kottapalli
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Publication number: 20150178206Abstract: An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M?) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: Jeffrey D. Chamberlain, Vedaraman Geetha, Robert G. Blankenship, Yen-Cheng Liu, Adrian C. Moga, Herbert H. Hum, Sailesh Kottapalli
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Publication number: 20150081977Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.Type: ApplicationFiled: November 21, 2014Publication date: March 19, 2015Inventors: SAILESH KOTTAPALLI, HENK G. NEEFS, RAHUL PAL, MANOJ K. ARORA, DHEEMANTH NAGARAJ
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Publication number: 20150006834Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.Type: ApplicationFiled: June 29, 2013Publication date: January 1, 2015Inventors: Subramanya R. DULLOOR, Sanjay KUMAR, Rajesh M. SANKARAN, Gilbert NEIGER, Richard A. UHLIG, Robert S. CHAPPELL, Joseph NUZMAN, Kai CHENG, Sailesh KOTTAPALLI, Yen-Cheng LIU, Mohan KUMAR, Raj K. RAMANUJAN, Glenn J. HINTON
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Patent number: 8918592Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.Type: GrantFiled: December 27, 2013Date of Patent: December 23, 2014Assignee: Intel CorporationInventors: Sailesh Kottapalli, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Dheemanth Nagaraj
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Publication number: 20140337857Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.Type: ApplicationFiled: July 24, 2014Publication date: November 13, 2014Inventors: Sailesh Kottapalli, John H. Crawford
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Publication number: 20140281270Abstract: Methods and apparatus relating to directory based coherency to improve input/output write bandwidth in scalable systems are described. In one embodiment, a first agent receives a request to write data from a second agent via a link and logic causes the first agent to write the directory state to an Input/Output Directory Cache (IODC) of the first agent. Additionally, the logic causes the second agent to send data from a modified state to an exclusive state using write back to the first agent, while allowing the data to remain cached exclusively in the second agent and also enabling the deallocation of the IODC entry in the first agent. Other embodiments are also disclosed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Henk G. Neefs, Ganesh Kumar, Vedaraman Geetha, Jeffrey D. Chamberlain, Sailesh Kottapalli, Jeffrey S. Wilder