Abstract: A combined, parallel adaptive equalizer/echo canceller is disclosed. The equalizer/canceller receives at least one input signal which is split into n taps. The n taps are multiplied by corresponding n tap coefficients to produce n tap output signals. The n tap output signals are then processed through an additive pipeline to produce a filter output signal. The additive pipeline provides low latency by processing the nth most recent tap output signal n clock cycles from the filter output signal. The combined FIR filter structure is made fully adaptive using delayed LMS coefficient adaptation. Tap coefficients are updated using an error signal and delayed versions of the input signal. The error signal is a product of a calculated error and a negative adaptation factor. The delay is equal to a sum of n+1 cycles.

Abstract: A state synchronized cipher text scrambler is disclosed. The state synchronized cipher text scrambler enables multiple data streams to be scrambled in parallel in such a way that the data streams are uncorrelated with respect to each other and there is a large fixed delay relationship between the scrambler bits over the multiple streams. This enables a receiver to correctly identify the ordering of the multiple data streams with respect to each other automatically, correct for any polarity or wire-swap misconnections and align the received multiple data streams despite differential delays between the data streams.

Abstract: A gigabuffer repeater transmission protocol minimizes the amount of buffering necessary at the repeater. Minimum buffer memory requirements are accomplished by using the initial portion of the data packet as the "Request to Send" message and waits, if necessary, until it receives a "Clear to Send" signal from the repeater. Thus, the repeater retains the majority of the buffering at the source of the data, where it is typically cheapest. Further, the repeater transmission scheme can be applied to centrally arbitrated repeaters.

Abstract: A packetized trellis coder and method for providing error correction coding of IEEE 802.3 frame formatted Ethernet packets for transmission at one gigabit per second (Gbps) over twisted-pair wiring. The error correction code protects each byte of the ethernet frame with a parity bit constructed using a convolutional encoder such that a maximum likelihood sequence estimation at the receiver using a Viterbi decoder will result in a significant receiver performance gain. At the end of the Ethernet packet, the trellis coder restores the states of the convolutional encoder to a known value (state 0) before beginning Idle transmission so that the Viterbi decoder at the receiver can read off the end-of-packet symbols without any performance penalty. The mapping and the inverse mapping from raw data bits to symbols and vice-versa can be implemented with simple gates due to algorithmic symbol mapping of a 4-D trellis code via 1-D partitioning.

Abstract: A method of performing motion estimation is disclosed which reduces the memory bandwidth requirements and simplifies the computations for performing block matching. First, multibit pixel values of frames are converted to single bit pixel values. Then, a previous frame of single bit pixel values and a reference frame of single bit pixel values are stored. To find a best match block in the previous frame, sum-of-absolute differences of pixel values between the reference frame and a block in a search area within the previous frame are compared. Finally, a motion vector representing the difference between the reference block and the best matched block in the previous frame is calculated. The value of a reference pixel is thresholded with respect to a low-pass filtered average value around the reference pixel. The reference pixel is substituted by the average value of the neighboring pixels. The multibit pixel values may be eight bit intensity values.

Abstract: A state synchronized cipher text scrambler is disclosed. The state synchronized cipher text scrambler enables multiple data streams to be scrambled in parallel in such a way that the data streams are uncorrelated with respect to each other and there is a large fixed delay relationship between the scrambler bits over the multiple streams. This enables a receiver to correctly identify the ordering of the multiple data streams with respect to each other automatically, correct for any polarity or wire-swap misconnections and align the received multiple data streams despite differential delays between the data streams.

Abstract: A packetized trellis coder and method is disclosed for providing error correction coding of IEEE 802.3 frame formatted Ethernet packets for transmission at one gigabit per second (Gbps) over twisted-pair wiring has been disclosed. The error correction code protects each byte of the ethernet frame with a parity bit constructed using a convolutional encoder such that a maximum likelihood sequence estimation at the receiver using a Viterbi decoder will result in a significant receiver performance gain. At the end of the Ethernet packet, the trellis coder restores the states of the convolutional encoder to a known value (state 0) before beginning Idle transmission so that the Viterbi decoder at the receiver can read off the end-of-packet symbols without any performance penalty. The mapping and the inverse mapping from raw data bits to symbols and vice-versa can be implemented with simple gates due to algorithmic symbol mapping of a 4-D trellis code via 1-D partitioning.