Abstract: A method of passivating copper interconnects is disclosed. A freshly electrodeposited copper interconnect such as formed as via/trench structures in semiconductor manufacturing is chemically converted to passivating surface of copper tungstate or copper chromate either through MOCVD reaction with vapors of tungsten or chromium alkoxides, or by pyrolytic reaction with tungsten or chromium carbonyl in the presence of O.sub.2. The copper interconnect having the formed passivation service is then chemically mechanically polished. The process can be used with various manufacturing processes, including single and dual damascene processes.

Abstract: An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.

Abstract: The present invention provides a method of forming an alloy interconnect in an integrated circuit having a dielectric layer with an opening formed therein. In an advantageous embodiment, the method comprises the steps of forming a metal alloy within the opening. The metal alloy comprises at least a first and a second metal with the first metal selected from a Group 13 metal and having a melting point substantially lower than a melting point of the second metal and the dielectric. This particular method further comprises the steps of subjecting the first and second metals to a temperature sufficient to melt the first metal and reflow the metal alloy.

Abstract: A semiconductor device and a method of manufacture therefor. The semiconductor device includes: (1) a substrate having a recess therein, (2) an aluminum-alloy layer located over at least a portion of the substrate and filling at least a portion of the recess and (3) a protective metal layer at least partially diffused in the aluminum-alloy layer, the metal protective layer having a high affinity for oxygen and acting as a sacrificial target for oxygen during a reflow of the aluminum-alloy layer.

Abstract: An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.

Abstract: Tungsten plugs are formed by passivating a substrate having a contact hole with SiH.sub.4, forming a nucleation layer on the passivated substrate by reducing WF.sub.6 with SiH.sub.4 at relatively low pressures and depositing tungsten to substantially fill the contact hole by reducing WF.sub.6 with H.sub.2 at relatively high pressures. Alternatively, rapid thermal annealing is used to cure pinhole defects in a titanium nitride layer on a substrate to avoid the formation of unwanted tungsten volcanoes.

Abstract: A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems. The selection of the thickness of the second sublayer to be a major portion and the inclusion of barrier layers are also described.

Abstract: In an integrated circuit, an opening (e.g., via or window) is filled with an Al-based plug which has essentially a <111> orientation and comprises at most three grains. These characteristics are achieved by first depositing a texture control Ti layer having substantially a (002) basal plane orientation followed by at least three Al-based sublayers. The grain sizes and deposition conditions are controlled in such a way that during deposition of the third sublayer, the microstructure of the plug adjusts itself to produce a single grain (or at most three).

Abstract: Tungsten plugs are formed in a manner which avoids the formation of unwanted tungsten volcanoes by depositing at least three and preferably five to seven layers of tungsten within a contact hole to form a layered plug. In particularly useful embodiments, the layers are deposited at alternating fast and slow rates of deposition.

Abstract: Electrical discontinuities in a silicide formed on a patterned surface are prevented by forming metal fillets in the recesses of the patterned polysilicon covered surface, and then depositing a metal layer and reacting with silicon to form the silicide. The fillet provides extra metal at a place where there is typically a deficiency in conventional deposition techniques.