Abstract: An integrated circuit device is disclosed that includes an sense amplifier having first and second input terminals, a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier, and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously.

Abstract: An integrated circuit device is disclosed that includes an sense amplifier having first and second input terminals, a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier, and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously.

Abstract: An amplifier circuit is disclosed having an amplifier with first and second input terminals. The amplifier circuit includes a first compensation capacitor coupled to the first input terminal and having a first capacitance, a second compensation capacitor coupled to the second input terminal and having a second capacitance, a first transistor coupled between the first compensation capacitor and a reference voltage and having a gate terminal that receives a first control signal, and a second transistor coupled between the second compensation capacitor and the reference voltage and having a gate terminal for receiving a second control signal. The amplifier circuit includes a programmable latch circuit arranged to provide the first and second control signals, wherein the first and second transistors are of the same conductivity type, and the first control signal and the second control signal are complementary signals with respect to each other.

Abstract: A memory, such as a non-volatile ferroelectric memory, including both error correction coding (ECC) capability and redundant memory cells. During the system operating life of the memory, upon ECC decoding determining that a symbol read from the memory array at an address cannot be corrected, the failed memory cells are identified, and redundancy enabled to replace those failed cells if available. Redundant columns may be partitioned by row address, to allow the same column of redundant cells to replace bits in different columns for different portions of the memory. Dynamic redundancy is provided by the disclosed embodiments, extending the reliability of the memory during its system operating life.

Abstract: An amplifier circuit is disclosed having an amplifier with first and second input terminals. The amplifier circuit includes a first compensation capacitor coupled to the first input terminal and having a first capacitance, a second compensation capacitor coupled to the second input terminal and having a second capacitance, a first transistor coupled between the first compensation capacitor and a reference voltage and having a gate terminal that receives a first control signal, and a second transistor coupled between the second compensation capacitor and the reference voltage and having a gate terminal for receiving a second control signal. The amplifier circuit includes a programmable latch circuit arranged to provide the first and second control signals, wherein the first and second transistors are of the same conductivity type, and the first control signal and the second control signal are complementary signals with respect to each other.

Abstract: An amplifier circuit is disclosed having an amplifier with first and second input terminals coupled to receive an input signal. A first compensation circuit is coupled to the first input terminal, and a second compensation circuit is coupled to the second input terminal. A programmable latch circuit is arranged to select one of the first and second compensation circuits.

Abstract: An amplifier circuit is disclosed having an amplifier with first and second input terminals coupled to receive an input signal. A first compensation circuit is coupled to the first input terminal, and a second compensation circuit is coupled to the second input terminal. A programmable latch circuit is arranged to select one of the first and second compensation circuits.

Abstract: A memory, such as a non-volatile ferroelectric memory, including both error correction coding (ECC) capability and redundant memory cells. During the system operating life of the memory, upon ECC decoding determining that a symbol read from the memory array at an address cannot be corrected, the failed memory cells are identified, and redundancy enabled to replace those failed cells if available. Redundant columns may be partitioned by row address, to allow the same column of redundant cells to replace bits in different columns for different portions of the memory. Dynamic redundancy is provided by the disclosed embodiments, extending the reliability of the memory during its system operating life.

Abstract: A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines.

Abstract: A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines.

Abstract: A ferroelectric random access memory (FRAM) with reduced cycle time. During a read cycle, plate line voltages are boosted to a voltage to both transfer charge from the selected row of FRAM cells to corresponding bit lines, and to fully polarize a data state in the selected FRAM cells. In one embodiment of the invention, the fully polarized data states is present in those cells that previously stored that data state; for those cells storing the opposite state, a write-back pulse is executed. In another embodiment of the invention, the fully polarized data state results for each of the selected memory cells, by applying a plate line boost voltage of a higher magnitude. Those cells that are to store the opposite data state, as may be determined following error correction, are written back with that data state.

Abstract: A ferroelectric random access memory (FRAM) with reduced cycle time. During a read cycle, plate line voltages are boosted to a voltage to both transfer charge from the selected row of FRAM cells to corresponding bit lines, and to fully polarize a data state in the selected FRAM cells. In one embodiment of the invention, the fully polarized data states is present in those cells that previously stored that data state; for those cells storing the opposite state, a write-back pulse is executed. In another embodiment of the invention, the fully polarized data state results for each of the selected memory cells, by applying a plate line boost voltage of a higher magnitude. Those cells that are to store the opposite data state, as may be determined following error correction, are written back with that data state.