Abstract: Methods, systems, and devices for improved techniques for partial writes are described. A memory device may include a non-volatile memory and a volatile memory configured to operate as a cache for the non-volatile memory. The memory device may receive, from a host device, a write command for a first data set provided by the host device. Based on the write command, the memory device may store the first data set in a buffer coupled with a volatile memory. After storing the first data set in the buffer, the memory device may communicate to the volatile memory a set of data that includes the first data set and a second data set. The first data set and the second data may be associated with adjacent addresses for the volatile memory and may each have sizes smaller than a threshold size associated with the volatile memory.

Abstract: Methods, systems, and devices for an efficient turnaround policy for a bus are described. A device may include a memory and a bus for communicating with the memory. The device may operate the bus in a first direction, relative to the memory, that is associated with a first type of access command. The device may determine, for the memory, that a quantity of queued access commands of a second type are for one or more banks that have satisfied a timing constraint for activating different rows in a same bank. Based on determining that the quantity of queued access commands of the second type are for one or more banks that have satisfied the timing constraint, the device may operate the bus in a second direction, relative to the memory, that is associated with the second type of access command.

Abstract: Methods, systems, and devices for cache management in a memory subsystem are described. A device may determine to perform an eviction procedure for a bank of a volatile memory that operates as a cache for a non-volatile memory. The eviction procedure may save data from the bank of the volatile memory to the non-volatile memory. The device may determine an activity status for at least one buffer in a pool of buffers that are coupled with the volatile memory and the non-volatile memory. The device may select the at least one buffer in the pool of buffers for the eviction procedure for the bank of the volatile memory based at least in part on the activity status for that buffer.

Abstract: Methods, systems, and devices for efficient command scheduling for multiple memories are described. A device may be coupled with a non-volatile memory that may operate as main memory and a volatile memory that may operate as a cache for the non-volatile memory. The device may receive an access command from a host device. The device may determine the appropriate memory from multiple memories for servicing the access command and communicate the access command to the memory.

Abstract: Methods, systems, and devices for transaction management based on metadata are described. A host device may transmit a read command to a memory device. Based on the read command, the host device may receive a set of data from the memory device. The host device may also receive metadata associated with the set of data. Based on the metadata, the host device may determine whether the set of data is the data requested by the read command, data requested by a previous read command, or data unrequested by the host device, or some combination. If the set of data is the data requested by the read command or a previous read command, the host device may process the set of data accordingly. If the set of data is data unrequested by the host device, the host device may discard the set of data and retransmit the read command.

Abstract: Methods, systems, and devices for metadata management for a cache are described. An interface controller may include a first array and a second array that store metadata for a cache memory. The interface controller may receive an activate command associated with a row of the cache memory. In response to the activate command, the interface controller may communicate storage information for the row of the volatile memory from a first array to a first register. The interface controller may receive an access command associated with the row of the cache memory. In response to the access command and based on the storage information in the first register, the interface controller may communicate validity information for the row from a second array to the first register or dirty information for the row from the second array to a second register.

Abstract: Methods, systems, and devices for transaction management using metadata are described. In some examples, a memory device may include a volatile memory, and a non-volatile memory, which may have different access latencies. The memory device may receive from a host device a read command for data located at an address of the non-volatile memory. In response to the read command, the memory device and may determine whether the data is stored in the volatile memory. The memory device may then transmit, to the host device data and according to an expected latency, a set of data and an indication of whether the set of data was previously requested by the host device or unrequested by the host device. In some examples, the memory device may also transmit an identifier associated with the read command and a hash of the address.

Abstract: Methods, systems, and devices for memory wear management are described. A device may include an interface controller and a non-volatile memory. The interface controller may manage wear-leveling procedures for memory banks in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear-leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then transfer the data to the non-volatile memory so that the non-volatile memory can write the data to a second row of the memory bank.

Abstract: Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

Abstract: An improved apparatus and method for the protection of reset in systems with stringent safety goals that employ primary and shadow logic blocks with a lock-step checker to achieve functional safety, including those systems having very large fanout of primary and shadow reset signal trees. The disclosed apparatus and method support assertion of reset that is asynchronous to the system clock and deassertion of reset that is synchronous to the system clock. Shadow logic blocks have reset deasserted a fixed number of clock cycles after their respective primary logic blocks, thereby avoiding the requirement to synchronize the primary and shadow reset signal trees at each of their end points to ensure lock-step operation between the primary and shadow logic blocks.

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.