Patents by Inventor Sairam Agraharam

Sairam Agraharam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128256
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Robert L. SANKMAN, Sairam AGRAHARAM, Shengquan OU, Thomas J. DE BONIS, Todd SPENCER, Yang SUN, Guotao WANG
  • Patent number: 11887962
    Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: January 30, 2024
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Sairam Agraharam, Edvin Cetegen, Anurag Tripathi, Malavarayan Sankarasubramanian, Jan Krajniak, Manish Dubey, Jinhe Liu, Wei Li, Jingyi Huang
  • Patent number: 11817444
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Robert L Sankman, Sairam Agraharam, Shengquan Ou, Thomas J De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Patent number: 11804470
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 31, 2023
    Assignee: Intel Corporation
    Inventors: Xavier F. Brun, Kaizad Mistry, Paul R. Start, Nisha Ananthakrishnan, Yawei Liang, Jigneshkumar P. Patel, Sairam Agraharam, Liwei Wang
  • Patent number: 11791274
    Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Omkar G. Karhade, Nitin A. Deshpande, Jinhe Liu, Sairam Agraharam, Mohit Bhatia, Edvin Cetegen
  • Publication number: 20230317653
    Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Hongxia FENG, Xiaoxuan SUN, Amey Anant APTE, Dingying David XU, Sairam AGRAHARAM, Gang DUAN, Ashay DANI
  • Publication number: 20230238339
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Application
    Filed: March 30, 2023
    Publication date: July 27, 2023
    Inventors: Dae-Woo KIM, Sujit SHARAN, Sairam AGRAHARAM
  • Publication number: 20230223361
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Application
    Filed: February 24, 2023
    Publication date: July 13, 2023
    Inventors: Dae-Woo KIM, Sujit SHARAN, Sairam AGRAHARAM
  • Publication number: 20230197546
    Abstract: Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Omkar Karhade, Sairam Agraharam, Nitin Deshpande
  • Publication number: 20230197685
    Abstract: Microelectronic stacked die package structures formed according to some embodiments may include a first die comprising a first conductive layer over a substrate layer. A second die may be on the first conductive layer. A third die is on the second die. An edge region of the stacked die package structure comprises a first portion over a second portion, the first portion comprising edges of the third die, the second die, and the first conductive layer, and the second portion comprising the substrate layer of the first die, wherein the first portion comprises a curved profile, and the second portion comprises a substantially vertical profile.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Omkar Karhade, Sairam Agraharam
  • Publication number: 20230197637
    Abstract: Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Mohammad Enamul Kabir, Nitin Deshpande, Omkar Karhade, Arnab Sarkar, Sairam Agraharam, Christopher Pelto, Gwang-Soo Kim, Ravindranath Mahajan
  • Patent number: 11626372
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan, Sairam Agraharam
  • Publication number: 20230087367
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a die attach film (DAF), at the first surface of the first die, including through-DAF vias (TDVs), wherein respective ones of the TDVs are electrically coupled to respective ones of the first conductive contacts; a conductive pillar in the first layer; and a second die, in a second layer on the first layer, wherein the second die is electrically coupled to the second conductive contacts on the second surface of the first die and electrically coupled to the conductive pillar.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Applicant: Intel Corporation
    Inventors: Xiaoxuan Sun, Omkar G. Karhade, Dingying Xu, Sairam Agraharam, Xavier Francois Brun
  • Publication number: 20230093186
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor device. In selected examples, the semiconductor device may include two semiconductor dies, a redistribution layer, an interconnect bridge coupled between the two semiconductor dies and located vertically between the two semiconductor dies and the redistribution layer, and a metallic connection passing through the redistribution layer and coupled to one or more of the two semiconductor dies in a solder-free connection.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Tarek A. Ibrahim, Rahul N. Manepalli, Sairam Agraharam, Xiaoxuan Sun
  • Publication number: 20220270976
    Abstract: Disclosed herein are microelectronic assemblies including bridges, as well as related methods. In some embodiments, a microelectronic assembly may include a bridge in a mold material.
    Type: Application
    Filed: February 23, 2021
    Publication date: August 25, 2022
    Inventors: Xiaoxuan Sun, Purushotham Kaushik Muthur Srinath, Sairam Agraharam
  • Publication number: 20220231007
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Inventors: Robert L. SANKMAN, Sairam AGRAHARAM, Shengquan OU, Thomas J. DE BONIS, Todd SPENCER, Yang SUN, Guotao WANG
  • Publication number: 20220199480
    Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, Xiaoxuan Sun, Nitin A. Deshpande, Sairam Agraharam
  • Publication number: 20220199503
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Manish DUBEY, Guruprasad ARAKERE, Deepak KULKARNI, Sairam AGRAHARAM, Wei-Lun K. JEN, Numair AHMED, Kousik GANESAN, Amol D. JADHAV, Kyu-Oh LEE
  • Patent number: 11348911
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Sairam Agraharam, Shengquan Ou, Thomas J De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Publication number: 20220157803
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 19, 2022
    Inventors: Robert L. SANKMAN, Sairam AGRAHARAM, Shengquan OU, Thomas J DE BONIS, Todd SPENCER, Yang SUN, Guotao WANG