Abstract: Integrated circuit structures having pre-spacer-deposition cut gates and associated defect test structures are described. For example, an integrated circuit structure includes a first and second fin or vertical arrangement of horizontal nanowires. First and second gate stacks are over the first and second fin or vertical arrangement of horizontal nanowires, respectively. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A dielectric structure has first and second portions forming a gate spacer along sidewalls of the first and second gate stacks, respectively, and a third portion completely filling the gap, the third portion continuous with the first and second portions. The integrated circuit structure also includes an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel with the first gate stack and the second gate stack.

Abstract: Design of overlay-based front end defect quick turn test chip is described. In an example, an integrated circuit structure includes a device layer including a vertical stack of horizontal nanowires or a fin, a gate electrode over the vertical stack of horizontal nanowires or the fin, a conductive trench contact adjacent to the gate electrode, and a dielectric sidewall spacer between the gate electrode and the conductive trench contact. The integrated circuit structure also includes a metallization layer immediately above the device layer, the metallization layer including a first test pad and a second test pad.

Abstract: Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, and methods of fabricating adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. One or more gate stacks is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between adjacent ones of the first epitaxial source or drain structures and between adjacent ones of the second epitaxial source or drain structures.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

Abstract: An integrated circuit on a production die comprises a device under test (DUT) cell array formed in a fill region on the production die, the DUT cell array comprising a plurality of DUT transistor structures configured for voltage contrast (VC) detection of electrical opens on the production die. The DUT transistor structures comprise one or more vias that are not located on power lines or signal lines, such that the DUT transistor structures are not connected to each other or to the electrically functioning transistors. A guard ring buffer is formed at a transition between the active transistor region and the DUT cell array.

Abstract: A device under test (DUT) structure for voltage contrast (VC) detection of contact opens comprises a fin formed along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon.

Abstract: Embodiments of the present disclosure relate to in-line detection of electrical fails on integrated circuits. One embodiment is an apparatus including a device region with integrated circuits and a test region for in-line failure detection of the integrated circuits using an in-line voltage contrast test, the apparatus comprising: a substrate including a first area for the device region and a second different area for the test region; metal layers formed over both areas; wherein the integrated circuits are formed from first sections of the layers; and wherein a second section of an upper metal layer of the layers is segmented into test segments, each test segment to exhibit a predefined response during the in-line voltage contrast test depending on whether the test segment is shorted, or not, to the substrate and/or the second section of a gate layer of the layer. Other embodiments may be disclosed and/or claimed.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

Abstract: Embodiments disclosed herein include an apparatus for alignment detection. In an embodiment, the apparatus comprises a substrate, and a plurality of devices on the substrate, where each of the plurality of devices comprises a process monitor structure with different offsets from a target value. In an embodiment, a plurality of electrically conductive traces are on the substrate, where each of the plurality of electrically conductive traces has a first end and a second end opposite the first end, and where each of the plurality of electrically conductive traces is electrically coupled at the first end, respectively, with each of the plurality of devices. In an embodiment, the second end of the each of the plurality of electrical traces is within a scan area on the substrate, and where the each of the plurality of electrically conductive traces are not directly electrically coupled with each other.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

Abstract: Embodiments described herein may be related to apparatuses, systems, processes, and/or techniques for identifying device defects on a wafer substrate using voltage contrast techniques and electronic beam scans by scanning an area on a portion of the wafer that includes ends of a plurality of traces that extend from the scan area respectively to blocks on the wafer that include devices to be tested. During the electronic beam scan, ends of the plurality of traces within the scan area that are coupled with devices that are electrically shorted will appear bright, and those that are electrically open will appear dark. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for electrically coupling components of a transistor structure together in order to perform a voltage contrast test to determine opens and shorts within the transistor structure. In embodiments, trench contacts (TCN) within a transistor structure may be electrically coupled together with an electrical connection that is electrically isolated from a power rail. In other embodiments, TCN may be electrically coupled using P-type epitaxial layers on a P-type substrate. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates with non-merged spacers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric liner is in lateral contact with and completely surrounded by the first dielectric gate spacer and the second dielectric gate spacer.

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates with extensions are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric material is between and in lateral contact with the first dielectric gate spacer and the second dielectric gate spacer.

Abstract: Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.

Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.