Patents by Inventor Sairam Subramanian

Sairam Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411665
    Abstract: Self-aligned gate endcap (SAGE) architectures having vertical transistors with SAGE gate structures, and methods of fabricating SAGE architectures having vertical transistors with SAGE gate structures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having first fin sidewall spacers, and a second semiconductor fin having second fin sidewall spacers. A gate endcap structure is between the first and second semiconductor fins and laterally between and in contact with adjacent ones of the first and second fin sidewall spacers, the gate endcap structure including a gate electrode and a gate dielectric. A first source or drain contact is electrically coupled to the first semiconductor fin. A second source or drain contact is electrically coupled to the second semiconductor fin.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Walid M. HAFEZ, Sairam SUBRAMANIAN, Chia-Hong JAN
  • Publication number: 20200287015
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ
  • Publication number: 20200286891
    Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Sridhar GOVINDARAJU, Kiran CHIKKADI
  • Publication number: 20200286890
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ
  • Publication number: 20200103451
    Abstract: Embodiments of the present disclosure relate to in-line detection of electrical fails on integrated circuits. One embodiment is an apparatus including a device region with integrated circuits and a test region for in-line failure detection of the integrated circuits using an in-line voltage contrast test, the apparatus comprising: a substrate including a first area for the device region and a second different area for the test region; metal layers formed over both areas; wherein the integrated circuits are formed from first sections of the layers; and wherein a second section of an upper metal layer of the layers is segmented into test segments, each test segment to exhibit a predefined response during the in-line voltage contrast test depending on whether the test segment is shorted, or not, to the substrate and/or the second section of a gate layer of the layer. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Enlan YUAN, David SANCHEZ, Amit PALIWAL, Manish SHARMA, Sairam SUBRAMANIAN, Sagar SUTHRAM
  • Publication number: 20190304902
    Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez
  • Publication number: 20190304971
    Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON, Sairam SUBRAMANIAN
  • Publication number: 20190305111
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Sairam SUBRAMANIAN, Christopher KENYON, Sridhar GOVINDARAJU, Chia-Hong JAN, Mark LIU, Szuya S. LIAO, Walid M. HAFEZ
  • Publication number: 20190305112
    Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON
  • Patent number: 6539221
    Abstract: The present invention is a system for optimizing an existing wireless network and additions to an existing network. The system determines a value representing estimation of traffic in discrete bins within a geographic area. The traffic estimation includes a distribution of handover and new cell traffic based at least in part on the presence of a road in any bin or the proximity of a bin to a handover boundary. The cell coverage and carrier allocations of existing cells are adjusted in view of the traffic estimation.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: March 25, 2003
    Assignee: Nortel Networks Limited
    Inventors: Mini Vasudevan, Carlos Garcia, Chang Yu, Hakan Ernam, Will Egner, Sairam Subramanian, Kenni Rasmussen
  • Patent number: 6178163
    Abstract: In a LEO satellite system with the implementation of a virtual network, a method and a system are proposed for arranging an optimal route for data packets to travel. The method and system will diversify the traffic between satellites, and accordingly enhance the efficient use of the entire satellite system. An intermediary satellite is first selected between a source satellite and a destination satellite. Further, an optimal route is found among a plurality of shortest paths between the source satellite and the intermediary satellite, and subsequently another optimal route is found between the intermediary satellite and the destination satellite. Once an optimal route is determined, the route information can be encoded in the header segment of data packets.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: January 23, 2001
    Assignee: Northern Telecom Limited
    Inventors: Wei Yuan, Sairam Subramanian
  • Patent number: 6141552
    Abstract: The mobility of mobile subscribers within a wireless digital communications system is estimated based on highway maps and traffic data. Cells within the network are modelled as nodes connected by edges where neighboring cells are connected by roads. Each edge has two edge weight components representing traffic flow from one cell to the other and vice versa. The edge weight components are calculated from terrain factors based on the size or capacity of the roads connecting the two cells and the total traffic within the subject cell, which information may be obtained from commercial geographic databases and/or government agencies. The resulting edge weight represents an expected number of handoffs between the two cells. The problem of partitioning cells among available switches within the network is thus reduced to the purely mathematical problem of minimizing the total edge weights of edges intersected by the partition boundaries.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: October 31, 2000
    Assignee: Nortel Networks Corporation
    Inventors: Andrew Sendonaris, Hongyi Chen, Nikhil Jain, Seshagri Madhavapeddy, Sairam Subramanian
  • Patent number: 6138025
    Abstract: A method for distributing paging load in a multicell wireless communication system establishes a plurality of location areas, with each location area including at least one cell. A load limit is based upon the greatest number of pages that may be transmitted in a particular cell over a given time period for cells of the multicell wireless communication system is determined. A paging load for the cellular wireless communication system is determined based upon historical loading and/or simulations and projections. A plurality of location areas are determined so that the paging load is distributed among the plurality of location areas such that a partial paging load respective to each cell of the multicell wireless communication system is less than a respective load limit. Boundaries of the location areas are then chosen to substantially minimize registration load within the multicell wireless communication system.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: October 24, 2000
    Assignee: Nortel Networks Limited
    Inventors: Hee C. Lee, Wei Yuan, Sairam Subramanian, Sheng-Chou Lin
  • Patent number: 6094580
    Abstract: Provided herein is a computer-implemented method for generating an optimized cellular-network cell-site plan for an area. A plurality of cellular-traffic demand nodes distributed across the area is provided. Each cellular-traffic demand node of the plurality of cellular-traffic demand nodes has an associated weighting characteristics set. The plurality of nodes are consolidated into a plurality of centroids. Each centroid represents a number of nodes that come within a traffic threshold. A potential cell site is positioned on each of the centroids. Each potential cell site has an associated base-transmitter-station parameter characteristics set. The demand node coverage of each potential cell site is determined with respect to a signal strength of the potential cell site. From the plurality of potential cell sites a minimized cell-site subset is selected while maintaining sufficient cellular service coverage of the plurality of demand nodes.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: July 25, 2000
    Assignee: Nortel Networks Corporation
    Inventors: Chang Yu, Sairam Subramanian, Andrew Sendonaris, Sheng-Chou Lin, Mohamed Landolsi, Nikhil Jain, Seshu Madhavapeddy, Stone Tseng, Venugopal Veeravalli
  • Patent number: 6085335
    Abstract: A self engineering system includes a data acquisition module, a self engineering engine, and a control module. The data acquisition module couples to the communication system and receives current operating data of the communication system. The self engineering engine receives the current operating data and determines new operating parameters of the communication system based upon the current operating data and current operating parameters. The control module implements the new operating parameters within the communication system. The self engineering system may include an expert system that receives the current operating data and, based upon the current operating data and the current operating parameters of the communication system, produces the new operating parameters. The expert system includes a fact library, a knowledge base and an inference engine. The fact library includes configuration data, historical operating data, the current operating parameters and proposed operating parameters.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: July 4, 2000
    Assignee: Nortel Networks Limited
    Inventors: Surnjani Djoko, Hua Jiang, Hee C. Lee, Sairam Subramanian, Seshagiri Madhavapeddy, Kalyan Basu
  • Patent number: 6055433
    Abstract: A data processing system implements a load balancing methodology which recognizes the effects that multiple, mobile subscribers have within a wireless communications network. During execution of this load balancing methodology, a rehoming operation is executed at a telephone central office to move some subscribers in a network to a new home mobile switching center with a minimum number of rehoming steps. To perform this rehoming operation, a mobile switching center in a network which has a highest load is selected first. Mobile switching centers which have a load lower than a network average load are considered to be candidates for a rehome destination. All subscriber groups homed to the highest loaded mobile switching center are evaluated to determine whether or not a rehoming operation using this subscriber group would provide a highest benefit and give a lowest standard deviation of loads among mobile switching centers after the rehome operation is selected.
    Type: Grant
    Filed: April 3, 1997
    Date of Patent: April 25, 2000
    Assignee: Northern Telecom Limited
    Inventors: Wei Yuan, Surnjani Djoko, Sairam Subramanian, Seshu Madhavapeddy, Payam Maveddat
  • Patent number: 6047186
    Abstract: The foregoing objects are achieved as is now described. Provided are a method and system for utilization with wireless communications systems having a cellular architecture covering a geographic area. The method and system accomplish their objects via the following. The geographic area is defined. One or more pairs of the sectors within the defined geographic area wherein a weak connection zone exists are determined. The geographic area is decomposed into two or more sub-areas wherein each sub-area is isolated from other sub-areas by the determined one or more pairs of sectors having a weak connection zone. A first of the sub-areas is selected. Frequency groups are assigned to each sector within the first selected sub-area such that signal to noise ratio is optimized. Thereafter, a second of the sub-areas is selected. One or more sectors within the second selected one of the sub-areas which are linked to sectors within the first selected sub-area are selected.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: April 4, 2000
    Assignee: Nortel Networks Corporation
    Inventors: Chang Yu, Xu Han, Seshagiri Rao Madhavapeddy, Sairam Subramanian
  • Patent number: 5907810
    Abstract: A method for reducing the paging load in a cellular communication system is described. The cell C with the largest paging load L is first identified. Since this cell is usually included in more than one paging zone, the paging zones including cell C are identified. Thereafter, cell C is removed tentatively from each identified zone and a ratio R calculated which represents the decrease in loading on cell C due to being removed from zone z divided by the maximum increase in loading on any other cell in the network. The zone for which the ratio R is the largest is the best candidate for removing cell C therefrom. After doing so tentatively, the cell C' with the largest paging load L' thereon is identified. If the loading L is greater than L', cell C is removed permanently from the zone having the highest ratio R therefor and the process is repeated until L' is greater than L at which point the process is stopped without removing cell C from the zone with the highest ratio R.
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: May 25, 1999
    Assignee: Northern Telecom Limited
    Inventors: Sairam Subramanian, Seshu R. Madhavapeddy, Alexander J. Montoya, Hee C. Lee, Steven J. Currin, Falguni Sarkar
  • Patent number: 5887156
    Abstract: Various operational measurements of a network element are determined in real time. These measurements are used to determine the call carrying capacity of the elements and the reaction of the network element to various call loads. Models of the network elements are generated from the operational measurements. Using an element's model, the network's reaction to various changes in a particular element can be determined without complex and expensive engineering work.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: March 23, 1999
    Assignee: Northern Telecom Limited
    Inventors: Sairam Subramanian, Seshagiri Madhavapeddy, Alexander J. Montoya