Abstract: A phase frequency detector with two stages of operation; each stage containing two D flip-flops. Each D flip-flop is interconnected to eliminate detection dead zone while avoiding glitches and incorrect output conditions for fast phase locked loop convergence and wide-band applications.

Abstract: A phase frequency detector with two stages of operation; each stage containing two D flip-flops. Each D flip-flop is interconnected to eliminate detection dead zone while avoiding glitches and incorrect output conditions for fast phase locked loop convergence and wide-band applications.

Abstract: A pipelined delta-sigma modulator (PDSM) analog to digital converter (ADC) architecture is disclosed where each stage of the pipelined ADC includes a delta sigma modulator with a digital low pass filter and a corresponding analog low pass filter that precisely matches the digital low pass filter. An error signal is generated at each stage based on the difference of the low pass filtered analog input and the low pass filtered digital output of the delta sigma modulator (after converting to an analog signal). The digital outputs of each stage are passed through the appropriate low pass filter stages so all digital signals have been subjected to the same filtering prior to combining in a digital error correction circuit. The present invention also uses a compensation filter to correct any errors in the pass band caused by the low pass filtering and to help reject unwanted noise outside the pass band.

Abstract: A pipelined delta-sigma modulator (PDSM) analog to digital converter (ADC) architecture is disclosed where each stage of the pipelined ADC includes a delta sigma modulator with a digital low pass filter and a corresponding analog low pass filter that precisely matches the digital low pass filter. An error signal is generated at each stage based on the difference of the low pass filtered analog input and the low pass filtered digital output of the delta sigma modulator (after converting to an analog signal). The digital outputs of each stage are passed through the appropriate low pass filter stages so all digital signals have been subjected to the same filtering prior to combining in a digital error correction circuit. The present invention also uses a compensation filter to correct any errors in the pass band caused by the low pass filtering and to help reject unwanted noise outside the pass band.