Patents by Inventor Sajith K. A.

Sajith K. A. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect Congestion Reduction for Memory-Mapped Peripherals
    Publication number: 20130290582
    Abstract: A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.
    Type: Application
    Filed: April 25, 2012
    Publication date: October 31, 2013
    Applicant: LSI CORPORATION
    Inventors: Srinivasa Rao Kothamasu, Debjit Roy Choudhury, Dharmesh Kishor Tirthdasani, Sajith K. A., Jean Jacob