Patents by Inventor Sajjad PARVIN

Sajjad PARVIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Perfect detection of concurrent faults in CMOS circuits by exploiting reversible and preservative gates
    Patent number: 11307252
    Abstract: A method of perfect detection of concurrent faults in CMOS circuits, using reversible gates and preservative gates is provided. The concurrent faults occurring in the CMOS circuits are detected without being masked by the method. The method includes the following steps: Carrying out functions using the reversible gates and the preservative gates, transforming the reversible gates and the preservative gates into CMOS circuit equivalents.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 19, 2022
    Assignee: Istanbul Teknik Universitesi
    Inventors: Mustafa Altun, Sajjad Parvin
  • PERFECT DETECTION OF CONCURRENT FAULTS IN CMOS CIRCUITS BY EXPLOITING REVERSIBLE AND PRESERVATIVE GATES
    Publication number: 20210141015
    Abstract: A method of perfect detection of concurrent faults in CMOS circuits, using reversible gates and preservative gates is provided. The concurrent faults occurring in the CMOS circuits are detected without being masked by the method. The method includes the following steps: Carrying out functions using the reversible gates and the preservative gates, transforming the reversible gates and the preservative gates into CMOS circuit equivalents.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 13, 2021
    Applicant: Istanbul Teknik Universitesi
    Inventors: Mustafa ALTUN, Sajjad PARVIN