Abstract: A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.

Abstract: A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.

Abstract: A circuit for attenuating phase jitter on an incoming clock signal includes a digital frequency synthesizer, and a phase lock loop including a phase detector. The digital phase detector compares the phase relationship between an incoming signal and a clock signal generated by the digitally controlled frequency synthesizer and produces an output signal proportional to the phase difference. The output signal comprises both a direction indicator and a magnitude indicator for controlling the digitally controlled frequency synthesizer. One of a plurality of phases of a voltage controlled oscillator (VCO) are selected in response to the output signal to alter the frequency of the clock signal.

Abstract: A circuit for attenuating phase jitter on an incoming clock signal includes a digitally controlled oscillator, a phase lock loop including a phase detector, and a dithering circuit. The oscillator is capable of generating N discrete frequencies selectable through digitally controlled inputs controlling switched, capacitively-loaded amplifier stages. The phase lock loop provides a total of C.times.N.times.NB frequencies. The phase detector consists primarily of an up/down counter with an overflow/underflow limiter circuit. The dithering circuit modulates the oscillator signal to reduce inadequate rejection behavior when the incoming clock frequency is substantially the same as one of the N selectable frequencies of the oscillator divided down to match the frequency of the incoming clock.

Abstract: A timing recovery loop comprising a multi-point sampling phase comparator 10, a data independent smoothing filter 12, a command sequencer 14, a digitally controlled ring oscillator with clock phase selection 16, a clock divider 18, a sampling clock generation control 20, a bandwidth controlling filter 166, a sequential prioritizer 168, a quarter bit detector 170, and a filter 172. The timing recovery loop has a triple loop structure for improved jitter tolerance and bandwidth control. All three loops share the common components of the ring oscillator 16, the clock divider 18, the sampling clock generation 20, the sampling phase comparator 10, and the command sequencer 14. The remaining components are used among one or more of the loops.

Abstract: A device (16) for reducing the intrinsic low frequency jitter within a Digital Phase lock loop (17). A Digital Phase lock loop high speed clock signal (4) is produced by a multistage oscillator (5), producing a plurality of identical frequency signals, each differing in phase. An adjust signal (18) generated by the Digital Phase lock loop output clock signal (3) causes an adjacent phase angle to be selected as the high speed clock signal (4), thereby reducing the period of the clock signal (4) and, in effect, accelerating the high speed clock signal (4). The current state of the selected phase and the appropriate selection of adjacent phase is monitored by a ten stage shift register (20-29), the presence of a "high bit" within a particular shift register block causing selection of the individual phase (6-15) which serves as the input to that particular shift register stage. An error correction circuit (40) detects the presence of more or less than a single high bit within the shift register stages (20- 29).

Abstract: A digitally controlled timing recovery loop is comprised of a digitally controlled Phase Locked Loop (PLL) consisting of a phase detector, loop filter, and voltage controlled oscillator (VCO). The phase detector is a multi-point sampling phase comparator. The loop filter is comprised of a data independent smoothing filter and a command sequencer. The VCO is a digitally controlled ring oscillator with clock phase selection. The timing recovery loop tolerates a relatively large amount of incoming jitter and minimizes data dependent, ISI-induced, intrinsic jitter.