Patents by Inventor Sakae Funo

Sakae Funo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10008426
    Abstract: An etching method for detecting crystal defects, the method includes providing a substrate with an etchant containing hydrogen fluoride, nitric acid, hydrogen chloride, and water. A concave portion on a part having a crystal defect of the substrate is formed by the etchant. The concave portion is examined by a microscope to locate a position of the crystal defect.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: June 26, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takehiro Nakai, Norihiko Tsuchiya, Sakae Funo, Junichi Shimada, Youko Itabashi
  • Publication number: 20170154829
    Abstract: An etching method for detecting crystal defects, the method includes providing a substrate with an etchant containing hydrogen fluoride, nitric acid, hydrogen chloride, and water. A concave portion on a part having a crystal defect of the substrate is formed by the etchant. The concave portion is examined by a microscope to locate a position of the crystal defect.
    Type: Application
    Filed: September 1, 2016
    Publication date: June 1, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takehiro NAKAI, Norihiko TSUCHIYA, Sakae FUNO, Junichi SHIMADA, Youko ITABASHI
  • Patent number: 6163050
    Abstract: In a silicon substrate, impurity diffusion layers, serving as source and drain regions, are formed to be separated from each other. A gate insulation film is formed on the silicon substrate between these source and drain regions. The gate insulation film is a silicon oxide film containing Cl having concentration of more than 1.times.10.sup.18 atoms/cm.sup.3 and less than 2.times.10.sup.20 atoms/cm.sup.3, and the gate insulation film is formed on the silicon substrate by low-pressure CVD. A gate electrode, formed of a polysilicon layer, is formed on the gate insulation film. An inter-level insulation film is formed on a resultant structure. A contact hole is formed on each of the source and drain regions of the inter-level insulation film. A drain electrode is formed on the inter-level insulation film, and connected to the drain region through the contact hole. A source electrode is formed on the inter-level insulation film, and connected to the source region through the contact hole.
    Type: Grant
    Filed: November 4, 1997
    Date of Patent: December 19, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyoshi Hisatomi, Yuuichi Mikata, Sakae Funo, Katsunori Ishihara
  • Patent number: 5714399
    Abstract: In a silicon substrate, impurity diffusion layers, serving as source and drain regions, are formed to be separated from each other. A gate insulation film is formed on the silicon substrate between these source and drain regions. The gate insulation film is a silicon oxide film containing Cl having concentration of more than 1.times.10.sup.18 atoms/cm.sup.3 and less than 2.times.10.sup.20 atoms/cm.sup.3, and the gate insulation film is formed on the silicon substrate by low-pressure CVD. A gate electrode, formed of a polysilicon layer, is formed on the gate insulation film. An inter-level insulation film is formed on a resultant structure. A contact hole is formed on each of the source and drain regions of the inter-level insulation film. A drain electrode is formed on the inter-level insulation film, and connected to the drain region through the contact hole. A source electrode is formed on the inter-level insulation film, and connected to the source region through the contact hole.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: February 3, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyoshi Hisatomi, Yuuichi Mikata, Sakae Funo, Katsunori Ishihara